Device and method for evaluating a temperature
View Patent ↗A device having temperature evaluating capabilities, the device includes: (i) a temperature sensitive delay line that comprises multiple first type NMOS transistors and first type PMOS transistors; (ii) an configurable delay line that comprises second type NMOS transistors and second type PMOS transistors; wherein a process condition sensitivity of first type NMOS transistors and first type PMOS transistors substantially equals a process condition sensitivity of the second type NMOS transistors and second type PMOS transistors; wherein the configurable delay line is less sensitive to temperature than the temperature sensitive delay line; (iii) a phase detector, coupled to an output of the temperature sensitive delay line and to an output of the adjustable delay line, the phase detector is adapted to determine a difference between a delay introduced by the temperature sensitive delay line and a delay introduced by the adjustable delay line; and (iv) a controller, adapted to: (a) find a configuration of the configurable delay line that introduces a delay that substantially equals a delay introduced by the temperature sensitive delay line; and (b) determine a temperature of the temperature sensitive delay line in response to the found configuration.
1. A device having temperature evaluating capabilities, the device comprises:
a temperature sensitive delay line;
a configurable delay line,
wherein the configurable delay line is less sensitive to temperature than the temperature sensitive delay line; and
a controller, adapted to:
find a configuration of the configurable delay line that introduces a delay that substantially equals a delay introduced by the temperature sensitive delay line; and
determine a temperature of the temperature sensitive delay line in response to the found configuration.
2. The device according to claim 1 wherein the controller is adapted to find a reference configuration of the configurable delay line, wherein the controller, once configured in the reference configuration and in a known temperature, introduces a delay that substantially equals a delay introduced by the temperature sensitive delay line.
3. The device according to claim 2 wherein the controller determines the temperature of the temperature sensitive delay line by comparing between a current configuration of the configurable delay line and the reference configuration, and applying a linear mapping between temperatures and configurations of the configurable delay line.
4. The device according to claim 3 wherein the configurable delay line comprises multiple rough delay cells and multiple fine delay cells, wherein a rough delay cell introduces a delay that is much longer than the delay introduced by a fine delay element.
5. The device according to claim 3 wherein the temperature sensitive delay line comprises multiple delay cells, each delay cell comprises multiple large width CMOS transistors that form an inverter and a capacitor, wherein the inverter charges and discharges the capacitor.
6. The device according to claim 3 wherein the non-CMOS transistors are Dual Gate Oxide transistors.
7. The device according to claim 3 wherein the temperature sensitive delay line receives a first input signal, and the configurable delay line receives a second input signal;
wherein the second input signal is delayed in relation to the first input signal by a delay that is responsive to a minimal delay introduced by the temperature sensitive delay line.
8. The device according to claim 7 comprising an input signal generator that generates the second input signal by delaying the first input signal.
9. The device according to claim 1 further comprising:
a phase detector, coupled to an output of the temperature sensitive delay line and to an output of the configurable delay line, the phase detector is adapted to determine a difference between a delay introduced by the temperature sensitive delay line and a delay introduced by the configurable delay line; and
wherein the temperature sensitive delay line comprises multiple first type NMOS transistors and first type PMOS transistors,
wherein the configurable delay line comprises second type NMOS transistors and second type PMOS transistors, and
wherein a process condition sensitivity of first type NMOS transistors and first type PMOS transistors substantially equals a process condition sensitivity of the second type NMOS transistors and second type PMOS transistors.
10. The device according to claim 9 wherein the controller determines a temperature of the temperature sensitive delay line by comparing the found configuration of the configurable delay line with a reference configuration, and applying a linear mapping between temperatures and configurations of the configurable delay line.
11. The device according to claim 10 wherein the configurable delay line comprises multiple rough delay cells and multiple fine delay cells, wherein a rough delay cell introduces a delay that is much longer than the delay introduced by a fine delay element.
12. The device according to claim 10 wherein the temperature sensitive delay line comprises multiple delay cells, each delay cell comprises multiple large width CMOS transistors that form an inverter and a capacitor, wherein the inverter charges and discharges the capacitor.
13. The device according to claim 10 wherein the non-CMOS transistors are Dual Gate Oxide transistors.
14. The device according to claim 10 wherein the temperature sensitive delay line receives a first input signal, and the configurable delay line receives a second input signal;
wherein the second input signal is delayed in relation to the first input signal by a delay that is responsive to a minimal delay introduced by the temperature sensitive delay line.
15. The device according to claim 14 comprising an input signal generator that generates the second input signal by delaying the first input signal.
16. A device having temperature evaluating capabilities, the device comprises:
a temperature sensitive delay line that comprises multiple first type NMOS transistors and first type PMOS transistors;
a configurable delay line that comprises second type NMOS transistors and second type PMOS transistors
wherein a process condition sensitivity of first type NMOS transistors and first type PMOS transistors substantially equals a process condition sensitivity of the second type NMOS transistors and second type PMOS transistors;
wherein the configurable delay line is less sensitive to temperature than the temperature sensitive delay line;
a phase detector, coupled to an output of the temperature sensitive delay line and to an output of the configurable delay line, the phase detector is adapted to determine a difference between a delay introduced by the temperature sensitive delay line and a delay introduced by the configurable delay line; and
a controller, adapted to:
find a reference configuration of the configurable delay line;
find a current configuration of the configurable delay line that introduces a second delay that substantially equals a second delay introduced by the temperature sensitive delay line; and
determine a temperature of the temperature sensitive delay line in response to the found current configuration; and
an input signal generator that generates a second input signal by delaying a first input signal based on the reference configuration, a first delay of the configurable delay line, and a first delay of the temperature sensitive delay line, and the input signal generator provides the second input signal to the configurable delay line.
17. The device according to claim 16 wherein the configurable delay line comprises multiple rough delay cells and multiple fine delay cells, wherein a rough delay cell introduces a delay that is much longer than a delay introduced by a fine delay element.
18. The device according to claim 16 wherein the temperature sensitive delay line receives the first input signal, and wherein the second input signal is delayed in relation to the first input signal by a delay that is responsive to a minimal delay introduced by the temperature sensitive delay line.
19. The device according to claim 16 wherein the controller determines a temperature of the temperature sensitive delay line by comparing between the current configuration of the configurable delay line and the reference configuration, and applying a linear mapping between temperatures and configurations of the configurable delay line.
20. A device having temperature evaluating capabilities, the device comprises:
a temperature sensitive delay line;
a configurable delay line that is less sensitive to temperature than the temperature sensitive delay line; and
a controller, adapted to:
find a configuration of the configurable delay line that introduces a delay that substantially equals a delay introduced by the temperature sensitive delay line; and
determine a temperature of the temperature sensitive delay line by comparing the found configuration of the configurable delay line to a reference configuration, and applying a linear mapping between temperatures and configurations of the configurable delay line.