IP Library Granted Patent US 7,419,866
Granted Patent B2
US 7,419,866 · App. 11/375,893 · Granted Sep 2, 2008

Process of forming an electronic device including a semiconductor island over an insulating layer

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Quick Facts
Patent No.
US 7,419,866
App. No.
11/375,893
Granted
Sep 2, 2008
Kind
B2
Abstract

A process of forming an electronic device can include forming a patterned oxidation-resistant layer over a semiconductor layer that overlies a substrate, and patterning the semiconductor layer to form a semiconductor island. The semiconductor island includes a first surface and a second surface opposite the first surface, and the first surface lies closer to the substrate, as compared to the second surface. The process can also include forming an oxidation-resistant material along a side of the semiconductor island or selectively depositing a semiconductor material along a side of the semiconductor island. The process can further include exposing the patterned oxidation-resistant layer and the semiconductor island to an oxygen-containing ambient, wherein a first portion of the semiconductor island along the first surface is oxidized during exposing the patterned oxidation-resistant layer, the semiconductor island, and the oxidation-resistant material to an oxygen-containing ambient.

Claims (54)

1. A process of forming an electronic device comprising:

forming a first patterned oxidation-resistant layer over a semiconductor layer,

wherein the semiconductor layer overlies an insulating layer that overlies a base layer;

patterning the semiconductor layer to form a first semiconductor island, wherein:

the first semiconductor island includes a first surface and a second surface opposite the first surface;

substantially all of the first semiconductor island and abuts and overlies the insulating layer;

the first surface lies closer to the base layer, as compared to the second surface; and

the second surface is spaced apart from the insulating layer;

forming an oxidation-resistant material along a side of the first semiconductor island; and

exposing the first patterned oxidation-resistant layer, the first semiconductor island, and the oxidation-resistant material to a first oxygen-containing ambient, wherein a first portion of the first semiconductor island along the first surface is oxidized during exposing the first patterned oxidation-resistant layer, the first semiconductor island, and the oxidation-resistant material to the first oxygen-containing ambient.

2. The process of claim 1 , further comprising removing the first patterned oxidation-resistant layer after exposing the first patterned oxidation-resistant layer, the first semiconductor island, and the oxidation-resistant material to the first oxygen-containing ambient.

3. The process of claim 2 , further comprising removing the oxidation-resistant material after exposing the first patterned oxidation-resistant layer, the first semiconductor island, and the oxidation-resistant material to the first oxygen-containing ambient.

4. The process of claim 1 , wherein the first patterned oxidation-resistant layer and the oxidation-resistant material comprise a nitride.

5. The process of claim 1 , wherein exposing the first patterned oxidation-resistant layer, the first semiconductor island, and the oxidation-resistant material to the first oxygen-containing ambient is performed at a temperature of at least approximately 800° C.

6. The process of claim 1 , wherein exposing the first patterned oxidation-resistant layer, the first semiconductor island, and the oxidation-resistant material to the first oxygen-containing ambient is performed, such that the first portion of the first semiconductor island lies along substantially all of the first surface.

7. The process of claim 1 , wherein exposing the first patterned oxidation-resistant layer, the first semiconductor island, and the oxdation-resistant material to the first oxygen-containing ambient is performed, such that a thickness of the first semiconductor island, as measured in a direction substantially perpendicular to a primary surface of the base layer, is reduced.

8. The process of claim 7 , wherein:

patterning the semiconductor layer also forms a second semiconductor island, wherein:

the second semiconductor island includes a third surface and a fourth surface opposite the third surface; and

the third surface lies closer to the base layer, as compared to the fourth surface; and

exposing the first patterned oxidation-resistant layer, the first semiconductor island, and the oxidation-resistant material to first oxygen-containing ambient is performed, such that:

a second portion of the second semiconductor island lying along the third surface is oxidized; and

the second portion of the second semiconductor island lies along part, but not all, of the third surface.

9. The process of claim 1 , wherein:

patterning the semiconductor layer also forms a second semiconductor island including a third surface and a fourth surface opposite the third surface, wherein:

substantially all the second semi conductor island abuts and overlies the insulating item:

the third surface lies closer to the base layer, as compared to the fourth surface; and

the fourth surface is spaced apart from the insulating layer;

the process further comprises:

forming a second patterned oxidation-resistant layer that overlies the second semiconductor island, but does not overlie the first semiconductor island; and

exposing the second patterned oxidation-resistant layer, the first semiconductor island, and parts of the first patterned oxidation-resistant layer and the oxidation-resistant material to a second oxygen-containing ambient, wherein another portion of the first semiconductor island adjacent to the insulating layer is oxidized but the second semiconductor island is not significantly oxidized.

10. The process of claim 8 , wherein after exposing the first patterned oxidation-resistant layer, the first semiconductor island, and the oxidation-resistant material to the first oxygen-containing ambient, the second surface of the first semiconductor island and the fourth surface of the second semiconductor island lie at substantially a same elevation.

11. A process of forming an electronic device comprising:

forming a patterned oxidation-resistant layer over a semiconductor layer that overlies a substrate;

patterning the semiconductor layer to form a first semiconductor island, wherein:

the first semiconductor island includes a first surface and a second surface opposite the first surface; and

the first surface lies closer to the substrate, as compared to the second surface;

selectively depositing a semiconductor material along a side of the first semiconductor island; and

exposing the patterned oxidation-resistant layer, the first semiconductor island, and the semiconductor material to an oxygen-containing ambient, wherein a first portion of the first semiconductor island along the first surface is oxidized during exposing the patterned oxidation-resistant layer, the first semiconductor island, and the oxidation-resistant material to an oxygen-containing ambient.

12. The process of claim 11 , wherein selectively depositing comprises epitaxially growing a silicon layer at the side of the first semiconductor island.

13. The process of claim 11 , wherein selectively depositing comprises epitaxially growing a silicon-germanium layer at the side of the first semiconductor island.

14. The process of claim 13 , wherein during exposing the patterned oxidation-resistant layer, the first semiconductor island, and the semiconductor material to an oxygen-containing ambient, germanium from the silicon-germanium layer migrates into the first semiconductor island.

15. The process of claim 11 , wherein exposing the patterned oxidation-resistant layer, the first semiconductor island, and the semiconductor material to an oxygen-containing ambient is performed at a temperature of at least approximately 800° C.

16. The process of claim 11 , wherein exposing the patterned oxidation-resistant layer, the first semiconductor island, and the semiconductor material to an oxygen-containing ambient is performed, such that the first portion of the first semiconductor island lies along substantially all of the first surface.

17. The process of claim 16 , wherein patterning the semiconductor layer is performed such that the first semiconductor island has a lateral dimension no greater than approximately one micron.

18. The process of claim 17 , wherein the second surface of the first semiconductor island is not significantly oxidized during exposing the patterned oxidation-resistant layer, the first semiconductor island, and the semiconductor material to an oxygen-containing ambient.

19. The process of claim 17 , wherein:

patterning the semiconductor layer also forms a second semiconductor island, wherein:

the second semiconductor island includes a third surface and a fourth surface opposite the third surface; and

the third surface lies closer to the substrate, as compared to the fourth surface; and

exposing the patterned oxidation-resistant layer; the first semiconductor island, and the semiconductor material to an oxygen-containing ambient is performed, such that:

a second portion of the second semiconductor island lying along the third surface is oxidized; and

the second portion of the second semiconductor island lies along part, but not all, of the third surface.

20. The process of claim 19 , wherein patterning the semiconductor layer is performed such that the second semiconductor island does not have a lateral dimension of less than approximately one micron.

Assignments (27)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
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CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
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RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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