Patent Application

App. No. 12/242,622

Abstract

Claims (70)

1 . A method of packaging a semiconductor die comprising the steps of:

providing a flange;

coupling one or more active die to the flange with a lead-free die attach material;

after coupling the one or more active die to the flange, staking a leadframe to the flange;

electrically interconnecting the one or more active die and the leadframe with an interconnect structure; and

applying a plastic material over the flange, the one or more active die, the leadframe, and the interconnect structure.

2 . The method of claim 1 wherein:

the step of coupling the leadframe to the flange and the step of electrically interconnecting the one or more active die and the leadframe occur simultaneously with each other.

3 . The method of claim 1 wherein:

the step of coupling the leadframe to the flange further comprises keeping the leadframe and the flange electrically isolated from each other.

4 . The method of claim 1 wherein:

the step of providing the flange further comprises providing multiple flanges coupled together in a leadframe-type structure; and

after applying the plastic material, further comprising:

singulating leads of the leadframe; and

singulating the flange.

5 . The method of claim 1 wherein:

the step of coupling the one or more active die to the flange further comprises providing the lead-free die attach material with a melting temperature greater than approximately 250 degrees Celsius.

6 . The method of claim 1 wherein:

the step of coupling the leadframe to the flange further comprises coupling the leadframe to the flange such that a bottom surface of the leadframe is not co-planar with a bottom surface of the flange and such that a top surface of the leadframe is not co-planar with a top surface of the flange.

7 . The method of claim 1 wherein:

the step of coupling one or more active die to the flange further comprises coupling two or more high power, active die to the flange.

8 . The method of claim 1 further comprising:

coupling one or more passive die to the flange with an other lead-free die attach material, wherein the other lead-free die attach material is different from the lead-free die attach material.

9 . The method of claim 1 wherein:

the step of electrically interconnecting the one or more active die and the leadframe further comprises electrically interconnecting the one or more active die to the flange.

10 . A method of packaging a high power and high frequency semiconductor die comprising the steps of:

providing a heatsink;

providing at least two semiconductor die, wherein at least a first one of the at least two semiconductor die has at least one high power, active device and wherein at least a second one of the at least two semiconductor die has at least one passive device;

using a lead-free, gold silicon die attach to couple the at least two semiconductor die to the heatsink;

after the step of using a gold silicon die attach, mechanically staking a leadframe and the heatsink together;

using wire bonds to electrically interconnect the at least two semiconductor die to the leadframe;

overmolding a plastic material over the at least two semiconductor die, the gold silicon die attach, the wire bonds, and at least a portion of the leadframe; and

singulating leads of the leadframe.

11 . The method of claim 10 wherein:

the step of providing the heatsink further comprises providing the heatsink comprised of a first material and a second material;

the first material is more ductile and thermally conductive than the second material;

the second material is more rigid than the first material; and

the first material is closer to the at least two semiconductor die than the second material.

12 . The method of claim 11 wherein:

the step of mechanically staking further comprises mechanically staking the first and second materials of the heatsink together; and

after the step of mechanically staking, the leadframe and the heatsink are non-coplanar with each other.

13 . The method of claim 10 wherein:

the step of providing the heatsink further comprises providing the heatsink with at least one feature; and

the step of mechanically staking further comprises mechanically staking the leadframe to the at least one feature of the heatsink.

14 . The method of claim 13 wherein:

the at least one feature of the heatsink is a through-hole in the heatsink; and

the step of overmolding the plastic material further comprises using the through-hole in the heatsink as a mold lock for the plastic material.

15 . The method of claim 10 wherein:

the step of providing the at least two semiconductor die further comprises:

providing the at least the first one of the at least two semiconductor die without a passive device; and

providing the at least the second one of the at least two semiconductor die without an active device.

16 . The method of claim 15 wherein:

the step of providing the at least two semiconductor die further comprises providing an additional semiconductor die;

the additional semiconductor die has a first high power transistor and is devoid of a passive device; and

the at least one high power, active device of the first one of the at least two semiconductor die is a second high power transistor.

17 . The method of claim 10 wherein:

the step of providing the heatsink further comprises selectively plating the heatsink.

18 . The method of claim 10 wherein:

the step of using the lead-free, gold silicon die attach further comprises using a heated scrubbing process to attach the at least two semiconductor die to the heatsink.

19 . The method of claim 10 wherein:

the step of providing the heatsink further comprises providing a recess at a perimeter of a bottom surface of the heatsink;

the step of using the lead-free, gold silicon die attach further comprises coupling the at least two semiconductor die to a top surface of the heatsink;

the step of overmolding the plastic material further comprises overmolding the plastic material under the heatsink and in the recess of the bottom surface of the heatsink; and

further comprising bending the leads to form a surface mount package for the high power semiconductor die.

20 . A semiconductor component comprising:

a flange;

two or more active die coupled to the flange with a lead-free die attach material;

a leadframe and the flange staked together;

an interconnect structure electrically coupling together the two or more active die and the leadframe; and

a plastic packaging material over the flange, the two or more active die, the leadframe, and the interconnect structure.

Assignments (15)