Multiple block memory with complementary data path
View Patent ↗A memory has a first memory block, a second memory block, a data bus, a first sense amplifier, a second sense amplifier, a first circuit, and a second circuit. The first sense amplifier is coupled to the first memory block. The second sense amplifier is coupled to the second memory block. The first circuit is coupled to the data bus and the first sense amplifier. The first circuit switches from precharging the data bus to providing data when the first memory block is selected and is decoupled from the data bus in response to the first memory block being deselected. The second circuit is coupled to the data bus and the second sense amplifier. The second circuit switches from precharging the data bus to providing data when the second memory block is selected and is decoupled from the data bus in response to the second memory block being deselected.
1. A memory, comprising:
a first memory block;
a second memory block;
a data bus;
a first sense amplifier coupled to the first memory block;
a second sense amplifier coupled to the second memory block;
a first circuit, coupled to the data bus and the first sense amplifier, that switches from precharging the data bus to providing data in response to a first sense enable signal when the first memory block is selected and wherein the first circuit is decoupled from the data bus in response to the first memory block being deselected; and
a second circuit, coupled to the data bus and the second sense amplifier, that switches from precharging the data bus to providing data in response to a second sense enable signal when the second memory block is selected and is decoupled from the data bus in response to the second memory block being deselected.
2. The memory of claim 1 , wherein the data bus has a true line and a complementary line.
3. The memory of claim 2 further comprising:
a latch, coupled to the data bus that provides an output representative of data on the data bus.
4. The memory of claim 3 , wherein:
the first circuit has a first output and a second output that couple a positive power supply voltage to the true and complementary lines when precharging and that provide complementary data to the true and complementary lines when providing data; and
the second circuit has a first output and a second output that couple the positive power supply voltage to the true and complementary lines when precharging and that provide complementary data to the true and complementary lines when providing data.
5. The memory of claim 4 , further comprising:
a first P channel transistor having a first current electrode coupled to the true line, a gate coupled to the complementary line, and a second current electrode for receiving the positive power supply voltage; and
a second P channel transistor having a first current electrode coupled to the complementary line, a gate coupled to the true line, and a second current electrode for receiving the positive power supply voltage.
6. The memory of claim 4 , wherein:
the first sense amplifier amplifies complementary data from the first memory block; and
the second sense amplifier amplifies complementary data from the second memory block.
7. The memory of claim 6 further comprising a memory control circuit that provides a first block select signal that when active selects the first memory block and a second block select signal that when active selects the second memory block.
8. The memory of claim 7 further comprising:
a first block control circuit coupled to the memory control circuit that provides the first sense enable signal; and
a second block control circuit coupled to the memory control circuit that provides the second sense enable signal.
9. The memory of claim 1 further comprising;
a third memory block;
a third sense amplifier coupled to the third memory block;
a third circuit coupled to the data bus and the third sense amplifier that switches from precharging the data bus to providing data in response to a third sense enable signal when the third memory block is selected and is decoupled from the data bus in response to the third memory block being deselected.
10. The memory of claim 2 further comprising:
a first P channel transistor having a first current electrode coupled to the true line, a gate coupled to the complementary line, and a second current electrode; and
a second P channel transistor having a first current electrode coupled to the complementary line, a gate coupled to the true line, and a second current electrode coupled to the second current electrode of the first P channel transistor.
11. A method of operating a memory having a data bus, a first memory block, a second memory block, a first sense amplifier coupled to the first memory block, a second sense amplifier coupled to the second memory block, a first circuit coupled between the first sense amplifier and the data bus, and a second circuit coupled between the second sense amplifier and the data bus, comprising:
precharging the data bus through the first and second circuit;
selecting the first memory block and deselecting the second memory block in response to a clock signal;
terminating precharging the data bus through second circuit while maintaining precharging of the data bus through first circuit; and
providing data from the first memory block to the data bus through the first circuit and terminating precharging of the data bus through the first circuit in response to a first sense enable signal.
12. The method of claim 11 further comprising:
precharging the data bus through the first and second circuit in response to an end of active cycle signal;
selecting the second memory block and deselecting the first memory block in response to the clock signal;
terminating precharging the data bus through first circuit while maintaining precharging of the data bus through second circuit; and
providing data from the second memory block to the data bus through the second circuit and terminating precharging of the data bus through the second circuit in response to a second sense enable signal.
13. The method of claim 11 , wherein the step of precharging is further characterized by the data bus comprising a true line and a complementary line in which the true line and the complementary line are precharged to a positive voltage.
14. The method of claim 13 , wherein the step of providing data is further characterized by providing complementary data by pulling down the voltage on one of the true and complementary lines through the first circuit while applying the positive voltage through a third circuit to the other of the true and complementary lines.
15. The method of claim 14 further comprising providing an output signal of the memory through a latch coupled to the true and complementary lines.
16. A memory, comprising:
a first memory block enabled in response to a first block select signal and having complementary outputs;
a second memory block enabled in response to a second block select signal and having complementary outputs;
a data bus having a true line and a complementary line;
a first sense amplifier coupled to the complementary outputs of the first memory block, having a clock input responsive to a first sense enable signal, and having complementary outputs;
a second sense amplifier coupled to complementary outputs of the second memory block, having a clock input responsive to a second sense enable signal, and having complementary outputs;
a first tri-driver coupled to the complementary outputs of the first sense amplifier, having a clock input responsive to the first sense enable signal, and having complementary outputs coupled to the data bus, wherein the first tri-driver performs a function selected from the group consisting of precharging the data bus, providing a high impedance to the data bus, and providing complementary data on the data bus; and
a second tri-driver coupled to the complementary outputs of the second sense amplifier, having a clock input responsive to the second sense enable signal, and having complementary outputs coupled to the data bus, wherein the second tri-driver performs a function selected from the group consisting of precharging the data bus, providing a high impedance to the data bus, and providing complementary data on the data bus.
17. The memory of claim 16 further comprising:
a first P channel transistor having a first current electrode coupled to the true line, a gate coupled to the complementary line, and a second current electrode for receiving the positive power supply voltage; and
a second P channel transistor having a first current electrode coupled to the complementary line, a gate coupled to the true line, and a second current electrode for receiving the positive power supply voltage.
18. The memory of claim 16 further comprising a latch coupled to the true and complementary lines that provides an output of the memory.
19. The memory of claim 16 further comprising:
a memory control circuit that provides the first block select signal, the second block select signal, and a clock signal.
a first block control circuit coupled to the memory control circuit that provides the first sense enable signal; and
a second block control circuit coupled to the memory control circuit that provides the second sense enable signal.
20. The memory of claim 16 , wherein the first tri-driver provides complementary data by reducing a voltage on one of the true and complementary lines while providing a high impedance to the other of the true and complementary lines.