Semiconductor device structure and integrated circuit therefor
View Patent ↗A semiconductor device structure comprises a plurality of vertical layers and a plurality of conductive elements wherein the vertical layers and plurality of conductive elements co-operate to function as at least two active devices in parallel. The semiconductor device structure may also comprise a plurality of horizontal conductive elements wherein the structure is arranged to support at least two concurrent current flows, such that a first current flow is across the plurality of vertical conductive elements and a second current flow is across the plurality of horizontal conductive elements.
1. A semiconductor device structure comprising:
a plurality of horizontal conductive elements and a plurality of vertical layers having a plurality of vertical conductive elements wherein the semiconductor device structure supports at least two active devices in parallel within the same structure;
a first active device being a PN diode and is arranged to support at least two concurrent current flows such that a first current flow is across the plurality of vertical conductive elements and a second current flow is across the plurality of horizontal conductive elements;
wherein:
the plurality of horizontal conductive elements form a PNP transistor as a second active device comprising a ‘P’ doped region and an ‘N’ doped region located within a ‘P − ’ doped region; and
a terminal of the PN diode and an emitter of the PNP transistor are connected at a first node, and another terminal of the PN diode and a collector of the PNP transistor are connected at a second node.
2. The semiconductor device structure of claim 1 wherein the total current flow within the semiconductor device structure is a combination of at least the first current flow and the second current flow.
3. The semiconductor device structure of claim 2 wherein a combined total current flow within the semiconductor device structure provides a stable current flow for the semiconductor device.
4. The semiconductor device structure of claim 1 wherein the semiconductor structure is employed in a protection circuit to protect against parasitic effects.
5. The semiconductor device structure of claim 4 wherein the protection circuit is arranged to protect against electrostatic discharge or electromagnetic interference.
6. The semiconductor device structure of claim 1 wherein an N-type buried layer is located under the three doped regions.
7. The semiconductor device structure of claim 1 wherein a first ‘P + ’ doped region is implanted in the ‘P’ doped region and a second ‘P + ’ doped region and an ‘N + ’ doped region are implanted in the ‘N’ doped region.
8. The semiconductor device structure of claim 1 wherein two ‘P + ’ doped regions are implanted respectively in a first ‘P’ doped region and a second ‘P’ doped region.
9. The semiconductor device structure of claim 8 wherein a PNP transistor is composed of the second ‘P + ’ doped region as an emitter, the ‘N’ doped region as a base, and both the ‘P − ’ doped region and the ‘P’ doped region as a collector.
10. The semiconductor device structure of claim 8 wherein emitter, base and collector contacts are respectively placed on the second ‘P + ’ doped region, the ‘N + ’ doped region and the first ‘P + ’ doped region.
11. The semiconductor device structure of claim 8 wherein PN diode current is arranged to contribute to the transistor bias current.
12. The semiconductor device structure of claim 8 wherein a PNP transistor is composed of one of the ‘P’ doped regions as an emitter, the N-doped region as a base, and both the first ‘P’ doped region and second ‘P’ doped region as a collector.
13. The semiconductor device structure of claim 8 wherein a first voltage is arranged to increase after the first active device has surpassed a first threshold voltage and trigger the second active device when the increasing voltage reaches a second threshold voltage.
14. The semiconductor device structure of claim 8 wherein the first active device and the second active device are arranged to provide a low snapback voltage.
15. An integrated circuit comprising a semiconductor device structure according to claim 8 .
16. An electronic device comprising the integrated circuit according to claim 15 .
17. A semiconductor device comprising:
a plurality of horizontal conductive elements and a plurality of vertical layers having a plurality of vertical conductive elements wherein the semiconductor device structure supports at least two active devices in parallel within the same structure;
a first active device being a PN diode and is arranged to support at least two concurrent current flows such that a first current flow is across the plurality of vertical conductive elements and a second current flow is across the plurality of horizontal conductive elements;
wherein:
the plurality of horizontal conductive elements form a PNP transistor as a second active device comprising a ‘P’ doped region and an ‘N’ doped region located within a ‘P − ’ doped region; and
a base of the PNP transistor and an emitter of the PNP transistor are connected at a node.
18. The semiconductor device structure of claim 2 wherein a first ‘P + ’ doped region is implanted in the ‘P’ doped region and a second ‘P + ’ doped region and an ‘N + ’ doped region are implanted in the ‘N’ doped region.
19. The semiconductor device structure of claim 9 wherein a first voltage is arranged to increase after the first active device has surpassed a first threshold voltage and trigger the second active device when the increasing voltage reaches a second threshold voltage.
20. The semiconductor device structure of claim 17 wherein the semiconductor structure is employed in a protection circuit to protect against parasitic effects.