IP Library Granted Patent US 8,031,549
Granted Patent B2
US 8,031,549 · App. 12/233,913 · Granted Oct 4, 2011

Integrated circuit having boosted array voltage and method therefor

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,031,549
App. No.
12/233,913
Granted
Oct 4, 2011
Kind
B2
Abstract

An integrated circuit comprises a global power supply conductor, a plurality of circuit blocks, a plurality of voltage converters, and control logic. The global power supply conductor is configured to distribute a supply voltage. The circuit blocks are selectively coupled to the global power supply conductor. The plurality of voltage converters are coupled to the global power supply conductor. An output voltage of individual voltage converters of the plurality of voltage converters are selectively coupled to one or more of the plurality of circuit blocks. The control logic is configured to control the selective coupling of at least one of the supply voltage and the output voltage of individual voltage converters of the plurality of voltage converters to corresponding ones of the plurality of circuit blocks. Also, the control logic controls a magnitude of the output voltage of individual voltage converters of the plurality of voltage converters.

Claims (38)

1. An integrated circuit comprising:

a global power supply conductor configured to distribute a supply voltage;

a plurality of circuit blocks, the circuit blocks being selectively coupled to the global power supply conductor;

a plurality of voltage converters coupled to the global power supply conductor, wherein an output voltage of individual voltage converters of the plurality of voltage converters are selectively coupled to one or more circuit blocks of the plurality of circuit blocks; and

control logic configured to

(i) control the selective coupling of at least one of (i)(a) the supply voltage and (i)(b) the output voltage of individual voltage converters of the plurality of voltage converters to corresponding ones of the plurality of circuit blocks, and

(ii) control a magnitude of the output voltage of individual voltage converters of the plurality of voltage converters,

wherein the control logic independently controls the magnitude of the output voltage of individual voltage converters of the plurality of voltage converters according to local power supply requirements of corresponding one or more selectively coupled circuit blocks.

2. The integrated circuit of claim 1 , wherein the individual voltage converters are located physically proximate to the corresponding one or more selectively coupled circuit blocks.

3. The integrated circuit of claim 2 , wherein physically proximate comprises immediately adjacent.

4. The integrated circuit of claim 1 , wherein the supply voltage comprises a first voltage, and wherein the output voltage of an individual voltage converter comprises a second voltage, wherein the second voltage comprises a magnitude that is different than a magnitude of the first voltage.

5. The integrated circuit of claim 1 , wherein the plurality of voltage converters comprises charge pumps.

6. The integrated circuit of claim 5 , further wherein at least one of the circuit blocks includes a charge storage capacitor, and wherein the charge storage capacitor is coupled to the output voltage of a corresponding charge pump of the plurality of charge pumps.

7. The integrated circuit of claim 5 , further wherein the output voltage of individual charge pumps comprises a voltage magnitude greater than a magnitude of the supply voltage.

8. The integrated circuit of claim 1 , wherein the plurality of voltage converters comprise voltage regulators.

9. The integrated circuit of claim 1 , wherein the circuit blocks comprise memory circuits, the memory circuits including at least one memory array.

10. The integrated circuit of claim 9 , further wherein the memory circuits comprises static random access memory (SRAM).

11. The integrated circuit of claim 1 , wherein the control logic includes a control storage element having a number of bit fields, each bit field including one or more control bits adapted to provide a desired control of (i) the selective coupling and (ii) the magnitude of output voltage of individual voltage converters.

12. The integrated circuit of claim 11 , wherein the control logic further comprises a voltage detector per at least one circuit block of the plurality of circuit blocks, wherein the voltage detector is responsive to a control input and an input voltage to the corresponding at least one circuit block for producing a magnitude control signal that is input to the corresponding voltage converter, the integrated circuit further comprising:

at least one multiplexer per one or more circuit blocks of the plurality of circuit blocks, the at least one multiplexer having first and second inputs and an output, the first input being coupled to the global power supply conductor, the second input being coupled to the output voltage of an individual voltage converter of a corresponding one or more circuit blocks of the plurality of circuit blocks, and the output being coupled to the corresponding one or more circuit blocks of the plurality of circuit blocks.

13. The integrated circuit of claim 12 , wherein the plurality of voltage converters comprises charge pumps.

14. The integrated circuit of claim 13 , further wherein at least one of the circuit blocks includes a charge storage capacitor, and wherein the charge storage capacitor is coupled to the output voltage of a corresponding charge pump of the plurality of charge pumps.

15. The integrated circuit of claim 14 , further wherein the output voltage of individual charge pumps comprises a boost voltage having a magnitude greater than a magnitude of the supply voltage.

16. An integrated circuit comprising:

a global power supply conductor configured to distribute a supply voltage;

a plurality of circuit blocks, the circuit blocks being selectively coupled to the global power supply conductor;

a plurality of voltage converters coupled to the global power supply conductor, wherein an output voltage of individual voltage converters of the plurality of voltage converters are selectively coupled to one or more circuit blocks of the plurality of circuit blocks; and

control logic configured to (i) control the selective coupling of at least one of (i)(a) the supply voltage and (i)(b) the output voltage of individual voltage converters of the plurality of voltage converters to corresponding ones of the plurality of circuit blocks, and (ii) control a magnitude of the output voltage of individual voltage converters of the plurality of voltage converters,

wherein the control logic independently controls the magnitude of the output voltage of individual voltage converters of the plurality of voltage converters according to local power supply requirements of corresponding one or more selectively coupled circuit blocks, the control logic including a control storage element having a number of bit fields, each bit field including one or more control bits adapted to provide a desired control of (i) the selective coupling and (ii) the magnitude of output voltage of individual voltage converters.

17. A method for providing local supply voltages in an integrated circuit comprising:

configuring a global power supply conductor to distribute a supply voltage;

selectively coupling a plurality of circuit blocks to the global power supply conductor;

coupling a plurality of voltage converters to the global power supply conductor, wherein an output voltage of individual voltage converters of the plurality of voltage converters are selectively coupled to one or more circuit blocks of the plurality of circuit blocks; and

controlling, via control logic

(i) the selective coupling of at least one of (i)(a) the supply voltage and (i)(b) the output voltage of individual voltage converters of the plurality of voltage converters to corresponding ones of the plurality of circuit blocks, and

(ii) a magnitude of the output voltage of individual voltage converters of the plurality of voltage converters, wherein controlling includes independently controlling the magnitude of the output voltage of individual voltage converters of the plurality of voltage converters according to local power supply requirements of corresponding one or more selectively coupled circuit blocks.

18. The method of claim 17 , wherein controlling, via control logic, further comprises independently controlling the magnitude of the output voltage of individual voltage converters of the plurality of voltage converters according to local power supply requirements of corresponding one or more selectively coupled circuit blocks, wherein the control logic includes a control storage element having a number of bit fields, each bit field including one or more control bits adapted to provide a desired control of (i) the selective coupling and (ii) the magnitude of output voltage of individual voltage converters.

19. The method of claim 17 , wherein the plurality of voltage converters comprise charge pumps, further wherein at least one of the circuit blocks includes a charge storage capacitor, and wherein the charge storage capacitor is coupled to the output voltage of a corresponding charge pump of the plurality of charge pumps, and further wherein the output voltage of individual charge pumps comprises a boost voltage having a magnitude greater than a magnitude of the supply voltage.

Assignments (16)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0757 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →