Effective eFuse structure
View Patent ↗An electrically programmable fuse (eFuse) comprises a semiconductor layer, a silicide layer overlying the semiconductor layer, and first and second contact structures electrically coupled to the silicide layer. The first contact structure is configured to function as an anode and the second contact structure is configured to function as a cathode. The eFuse further comprises a back-gate structure disposed underneath the semiconductor layer in a back-gate structure region proximate the second contact structure, the back-gate structure region excluding a region proximate the first contact structure. Responsive to (i) a programming voltage potential supplied between the first and second contact structures and (ii) a voltage potential supplied to the back-gate structure, silicide of the silicide layer operates to migrate, with an enhanced migration, into the semiconductor layer from the cathode to the anode with an absence of silicide residue in at least the back-gate structure region of the semiconductor layer between the first and second contact structures.
1. An electrically programmable fuse (eFuse) comprising:
a semiconductor layer;
a silicide layer overlying the semiconductor layer;
a first contact structure electrically coupled to the silicide layer;
a second contact structure electrically coupled to the silicide layer, wherein the first contact structure functions as an anode and the second contact structure functions as a cathode; and
a back-gate structure disposed underneath the semiconductor layer in a back-gate structure region proximate the second contact structure, the back-gate structure region excluding a region proximate the first contact structure, and the back-gate structure is positioned at least partially directly underneath the second contact structure.
2. The apparatus of claim 1 , wherein responsive to (i) a programming voltage potential supplied between the first and second contact structures and (ii) a voltage potential supplied to the back-gate structure, silicide of the silicide layer operates to migrate, with an enhanced migration, into the semiconductor layer from the cathode to the anode with an absence of silicide residue in at least the back-gate structure region of the semiconductor layer between the first and second contact structures.
3. The apparatus of claim 1 , wherein the semiconductor layer comprises an amorphous semiconductor layer.
4. The apparatus of claim 1 , wherein the semiconductor layer comprises a polysilicon layer.
5. The apparatus of claim 1 , wherein the silicide comprises one selected from the group consisting of nickel silicide (NiSi), cobalt silicide (CoSi), and nickel platinum silicide (NiPtSi).
6. The apparatus of claim 1 , wherein the back-gate structure comprises a gate dielectric layer overlying a conductor.
7. The apparatus of claim 6 , further wherein responsive to a programming voltage potential (i) supplied between the first and second contact structures and (ii) supplied to the conductor, silicide of the silicide layer operates to migrate into the semiconductor layer from the cathode to the anode with an absence of silicide residue in at least the back-gate structure region of the semiconductor layer between the first and second contact structures.
8. The apparatus of claim 1 , wherein the back-gate structure comprises a gate dielectric layer overlying at least a portion of a resistor.
9. The apparatus of claim 8 , further wherein (i) responsive to (i)(a) a programming voltage potential supplied between the first and second contact structures and (i)(b) a Joule-heating voltage potential (V Joule-heating ) supplied across the resistor, silicide of the silicide layer operates to migrate, with an accelerated migration in response to Joule-heating by the resistor, into the semiconductor layer from the cathode to the anode with an absence of silicide residue in at least the back-gate structure region of the semiconductor layer between the first and second contact structures.
10. The apparatus of claim 9 , wherein the resistor comprises a doped semiconductor layer.
11. The apparatus of claim 1 , wherein the back-gate structure comprises a portion of a CMOS transistor.
12. The apparatus of claim 11 , wherein the portion of the transistor includes a gate dielectric, a channel region, a source region, and a drain region, wherein the gate dielectric overlies at least the channel region between the source region and the drain region.
13. The apparatus of claim 12 , further wherein (i) responsive to (i)(a) a programming voltage potential supplied between the first and second contact structures and (i)(b) a transistor voltage potential V DS supplied across the drain and source regions, the semiconductor and silicide layers collectively operate as a gate of the transistor for initiating silicide migration from the cathode to the anode with enhancement through self-heating of at least the channel region of the transistor under bias, further wherein (ii) responsive to a given percentage of silicide migration to the anode, the semiconductor and silicide layers no longer collectively operate as the gate of the transistor and current from the drain region to the source region of the transistor automatically terminates.
14. The apparatus of claim 13 , further wherein silicide of the silicide layer operates to migrate, with an enhanced migration in response to the self-heating, into the semiconductor layer from the cathode to the anode with an absence of silicide residue in at least the back-gate structure region of the semiconductor layer between the first and second contact structures.
15. The apparatus of claim 1 , wherein the silicide layer includes a first dimension between the first contact structure and the second contact structure, the first dimension extending along a principal direction of the silicide layer, and wherein the back-gate structure includes a first dimension extending from the second contact structure towards the first contact structure along the principal direction of the silicide layer by a distance on the order of twenty-five to seventy-five percent (25-75%) of the first dimension of the silicide layer.
16. The apparatus of claim 15 , further wherein the first dimension of the back-gate structure is equal to approximately fifty percent (50%) of the first dimension of the silicide layer.
17. An electrically programmable fuse (eFuse) comprising:
a semiconductor layer;
a silicide layer overlying the semiconductor layer;
a first contact structure electrically coupled to the silicide layer;
a second contact structure electrically coupled to the silicide layer, wherein the first contact structure functions as an anode and the second contact structure functions as a cathode; and
a back-gate structure disposed underneath the semiconductor layer in a back-gate structure region proximate the second contact structure, the back-gate structure region excluding a region proximate the first contact structure, and the back-gate structure is positioned at least partially directly underneath the second contact structure,
wherein the back-gate structure comprises one selected from the group consisting of (a) a gate dielectric layer overlying a conductor, (b) a gate dielectric layer overlying at least a portion of a resistor, and (c) a portion of a CMOS transistor, and
further wherein responsive to (i) a programming voltage potential supplied between the first and second contact structures and (ii) a voltage potential supplied to the back-gate structure, silicide of the silicide layer operates to migrate, with an enhanced migration, into the semiconductor layer from the cathode to the anode with an absence of silicide residue in at least the back-gate structure region of the semiconductor layer between the first and second contact structures.
18. The apparatus of claim 17 , wherein the silicide layer includes a first dimension between the first contact structure and the second contact structure, the first dimension extending along a principal direction of the silicide layer, and wherein the back-gate structure region includes a first dimension extending from the second contact structure towards the first contact structure along the principal direction of the silicide layer by a distance on the order of twenty-five to seventy-five percent (25-75%) of the first dimension of the silicide layer.
19. The apparatus of claim 18 , further wherein the first dimension of the back-gate structure is equal to approximately fifty percent (50%) of the first dimension of the silicide layer.
20. A method for implementing an electrically programmable fuse (eFuse) comprising:
forming a back-gate structure within an insulative layer;
forming a semiconductor layer overlying the back-gate structure;
forming a silicide layer overlying the semiconductor layer;
forming a first contact structure electrically coupled to the silicide layer; and
forming a second contact structure electrically coupled to the silicide layer, wherein the first contact structure functions as an anode and the second contact structure functions as a cathode, and wherein the back-gate structure is disposed underneath the semiconductor layer in a back-gate structure region proximate the second contact structure, the back-gate structure region excluding a region proximate the first contact structure, and the back-gate structure is positioned at least partially directly underneath the second contact structure.
21. The apparatus of claim 1 , wherein the back-gate structure includes a migration enhancement portion that is at least as wide as a width dimension of the semiconductor layer and the silicide layer in the back-gate structure region.
22. The apparatus of claim 1 , wherein the back-gate structure further includes first and second portions which do not directly underly the semiconductor layer and the silicide layer, the first portion includes a third contact structure electrically coupled to the back-gate structure and the second portion includes a fourth contact structure electrically coupled to the back-gate structure.
23. The apparatus of claim 1 , wherein the back-gate structure is disposed underneath and in contact with the semiconductor layer in the back-gate structure region.