IP Library Granted Patent US 7,943,988
Granted Patent B2
US 7,943,988 · App. 12/205,438 · Granted May 17, 2011

Power MOSFET with a gate structure of different material

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Quick Facts
Patent No.
US 7,943,988
App. No.
12/205,438
Granted
May 17, 2011
Kind
B2
Abstract

A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.

Claims (35)

1. A semiconductor device, comprising:

a semiconductor layer of a first conductivity type and a first doping concentration;

a first semiconductor region above a first portion of the semiconductor layer, wherein the first semiconductor region is of the first conductivity type and has a doping concentration less than the first doping concentration;

a gate dielectric on a top surface of the first semiconductor region;

a gate electrode on the gate dielectric, wherein the gate electrode comprises a center portion that comprises metal on the gate dielectric, a first silicon portion on the gate dielectric laterally adjacent to a first side of the center portion, and a second silicon portion on the gate dielectric laterally adjacent to a second side of the center portion in which the first side is opposite the second side;

a second semiconductor region comprising a first portion under the first silicon portion and the gate dielectric, wherein the second semiconductor region is of a second conductivity type different from the first conductivity type; and

a third semiconductor region laterally adjacent to the first portion of the second semiconductor region, wherein the third semiconductor region is of the first conductivity type.

2. The semiconductor device of claim 1 , wherein the first semiconductor region functions as a drain, the second semiconductor region functions as a channel, and the third semiconductor region functions as a source.

3. The semiconductor device of claim 1 , wherein the center portion comprises a silicide.

4. The semiconductor device of claim 3 , further comprising tungsten silicide on the first silicon portion and the second silicon portion.

5. The semiconductor device of claim 1 , wherein the first silicon portion and the second silicon portion comprise polysilicon.

6. The semiconductor device of claim 1 , wherein the second semiconductor region further comprises a second portion adjacent to the third semiconductor region under the third semiconductor region.

7. The semiconductor device of claim 6 , wherein the second portion of the second semiconductor region is over and spaced from a second portion of the semiconductor layer.

8. The semiconductor device of claim 7 , wherein the first semiconductor region has a second portion between the second portion of the second semiconductor region and the second portion of the semiconductor layer.

9. The semiconductor device of claim 1 , further comprising a fourth semiconductor region laterally adjacent to the third semiconductor region and in contact with the second semiconductor region, wherein the fourth semiconductor region is of the second conductivity type.

10. The semiconductor device of claim 9 , further comprising a metal-containing conductive layer on the fourth semiconductor region and the third semiconductor region.

11. The semiconductor device of claim 1 , further comprising:

a fourth semiconductor region comprising a first portion under the second silicon portion and the gate dielectric, wherein the fourth semiconductor region is of the second conductivity type; and

a fifth semiconductor region laterally adjacent to the first portion of the fourth semiconductor region, wherein the fifth semiconductor region is of the first conductivity type.

12. The semiconductor device of claim 1 , wherein the first conductivity type is N type and the second conductivity type is P type.

13. The semiconductor device of claim 1 , wherein the first and second silicon portions further comprise germanium.

14. The semiconductor device of claim 1 , wherein the first semiconductor region includes a first portion and a second portion, the first portion has a higher doping concentration of the first conductivity type than the second portion, the first portion being located above the second portion.

15. A semiconductor device, comprising:

a substrate having a first semiconductor layer and a second semiconductor layer over the first semiconductor layer, wherein the first and second semiconductor layer are of a first conductivity type and the first semiconductor layer has a higher doping concentration than the second semiconductor layer;

a first pair of semiconductor regions in the second semiconductor layer of a second conductivity type separated by a first distance, wherein the first pair of semiconductor regions extend from a top surface of the second semiconductor layer part way through the second semiconductor layer;

a second pair of semiconductor regions of the first conductivity type within the second semiconductor layer and separated by a second distance greater than the first distance;

a gate dielectric over a portion of the top surface of the second semiconductor layer; and

a gate electrode over the gate dielectric, wherein the gate electrode has a pair of silicon portions on the gate dielectric separated by a third distance less than the first distance and a metal-containing portion on the gate dielectric between the pair of silicon portions.

16. The semiconductor device of claim 15 , further comprising:

a third pair of semiconductor regions of the second conductivity type within the second semiconductor layer and separated by a fourth distance greater than the second distance.

17. The semiconductor device of claim 15 , wherein the silicon portions comprise polysilicon and the metal-containing portion comprises a silicide.

18. The semiconductor device of claim 15 , further comprising a conductor layer of tungsten silicide overlying the pair of silicon portions.

19. The semiconductor device of claim 1 wherein the second semiconductor region is not located under the center portion of the gate electrode.

20. The semiconductor device of claim 2 wherein the second semiconductor region is not located under the center portion of the gate electrode.

21. The semiconductor device of claim 15 wherein a first pair of semiconductor regions function as transistor channel regions and are not located under the metal containing portion of the gate electrode.

Assignments (20)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0757 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Dec 9, 2008
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 021936/0772 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2008
From: PHAM, DANIEL; NGUYEN, BICH-YEN
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 021779/0054 →