Concurrent programming and program verification of floating gate transistor
View Patent ↗A program voltage is applied to the drain electrode of a floating gate transistor to program the floating gate transistor. Concurrent with the application of the program voltage, a current based on the voltage at the source electrode of the floating gate transistor is compared with a threshold current to verify the programming of the floating gate transistor. When the bit cell current falls below the threshold current, the floating gate transistor is considered to be sufficiently programmed and the next floating gate transistor to be programmed is selected. Further, the program voltage supply emulates the selection circuitry used to select between the bit cells so as to model the voltage drop caused by the selection circuitry between the program voltage supply and the drain electrode of the floating gate transistor being programmed. The program voltage supply adjusts the output program voltage based on the modeled voltage drop.
1. A method comprising:
applying a first program voltage to a drain electrode of a first floating gate transistor coupled to a first bit line of a non-volatile memory;
determining a first current based on a voltage at a source electrode of the first floating gate transistor concurrent with the application of the first program voltage to the drain electrode of the first floating gate transistor; and
terminating the application of the first program voltage to the drain electrode of the first floating gate transistor in response to determining the first current to be less than a threshold current.
2. The method of claim 1 , further comprising:
applying a second program voltage to a drain electrode of a second floating gate transistor coupled to a second bit line of the non-volatile memory subsequent to terminating the application of the first program voltage;
determining a second current based on a voltage at a source electrode of the second floating gate transistor concurrent with the application of the second program voltage to the drain electrode of the second floating gate transistor; and
terminating the application of the second program voltage to the drain electrode of the second floating gate transistor in response to determining the second current to be less than the threshold current.
3. The method of claim 1 , further comprising:
adjusting the first program voltage based on an expected voltage drop between a source of the first program voltage and the drain electrode of the first floating gate transistor.
4. The method of claim 3 , wherein:
applying the first program voltage comprises generating the first program voltage using a charge pump; and
adjusting the first program voltage comprises:
determining a voltage drop across a circuit component that models a corresponding circuit component coupled between an output of the charge pump and the drain electrode of the first floating gate transistor; and
adjusting the first program voltage via the charge pump based on the voltage drop.
5. The method of claim 1 , wherein determining the first current comprises:
determining a first voltage drop across a first resistive element coupled to the source electrode, wherein the first voltage drop is representative of the first current.
6. The method of claim 5 , further comprising:
determining a second voltage drop across a second resistive element coupled to receive the threshold current, wherein the second voltage drop is representative of the threshold current; and
determining a relationship between the first current and the threshold current based on a comparison of the first voltage drop to the second voltage drop.
7. The method of claim 1 , wherein:
the first current represents a threshold voltage of the first floating gate transistor;
the current threshold represents a predetermined threshold voltage; and
the predetermined threshold voltage represents a predetermined program state of the first floating gate transistor.
8. The method of claim 7 , wherein the predetermined program state comprises a program state representative of a logic zero value.
9. In a non-volatile memory comprising a first bit line coupled to a drain electrode of a first floating gate transistor and a second bit line coupled to a drain electrode of a second floating gate transistor, a method comprising:
selecting the first bit line for programming;
continuously applying a first program voltage to the drain electrode of the first floating gate transistor until a first current based on a voltage of a source electrode of the first floating gate transistor is less than a threshold current;
selecting the second bit line for programming subsequent to applying the first program voltage to the drain electrode of the first floating gate transistor; and
continuously applying a second program voltage to the drain electrode of the second floating gate transistor until a second current based on a voltage of a source electrode of the second floating gate transistor is less than a second threshold current.
10. The method of claim 9 , wherein:
the first current is representative of a threshold voltage of the first floating gate transistor;
the second current is representative of a threshold voltage of the second floating gate transistor; and
the current threshold is representative of a predetermined threshold voltage.
11. The method of claim 9 , further comprising:
determining the first current based on a first voltage drop across a resistive element coupled to the source electrode of the first floating gate transistor; and
determining the second current based on a second voltage drop across a resistive element coupled to the source electrode of the second floating gate transistor.
12. The method of claim 9 , wherein applying the first program voltage comprises adjusting the first program voltage based on an expected voltage drop between a source of the first program voltage and the drain electrode of the first floating gate transistor.
13. The method of claim 12 , wherein applying the second program voltage comprises adjusting the second program voltage based on an expected voltage drop between the source of the first program voltage and the drain electrode of the second floating gate transistor.
14. The method of claim 9 , wherein the first program voltage is equal to the second program voltage.
15. A non-volatile memory comprising:
a program voltage supply comprising an output to provide a program voltage;
a bit cell array comprising a first bit line and a first floating gate transistor having a drain electrode coupled to the first bit line;
a program select module configured to couple the first bit line to the output of the program voltage supply in a first state and to decouple the first bit line from the output of the program voltage supply in a second state; and
a program verify module comprising an input coupled to a source electrode of the first floating gate transistor and an output configured to adjust the program select module between the first state and the second state in response to a first current based on a voltage at the source electrode.
16. The non-volatile memory of claim 15 , wherein the program voltage supply comprises:
an emulation circuit having an input coupled to the output of the program voltage supply, wherein the emulation circuit is configured to emulate a corresponding circuit of the program select module that is coupled between the output of the program voltage supply and the drain electrode of the first floating gate transistor; and
means for adjusting the program voltage based on a voltage drop across the emulation circuit.
17. The non-volatile memory of claim 15 , wherein the program verify module comprises:
a first resistive element coupled to the source electrode of the first floating gate transistor;
a second resistive element to receive a reference voltage, wherein the reference voltage is representative of the threshold current; and
a comparator to selectively adjusting the program select module between the first state and the second state based on a comparison of a first voltage drop across the first resistive element and a second voltage drop across the second resistive element.
18. The non-volatile memory of claim 15 , wherein:
the bit cell array comprises a second bit line and a second floating gate transistor having a drain electrode coupled to the second bit line;
the program select module is configured to couple the second bit line to the output of the program voltage supply in the second state and to decouple the second bit line from the output of the program voltage supply in the first state; and
the program verify module comprises an input coupled to a source electrode of the second floating gate transistor and an output to selectively disable the program select module in response to a second current based on a voltage at the source electrode of the second floating gate transistor.
19. The non-volatile memory of claim 15 , wherein the non-volatile memory is a flash memory.