IP Library Granted Patent US 8,020,017
Granted Patent B2
US 8,020,017 · App. 12/192,683 · Granted Sep 13, 2011

Management of power domains in an integrated circuit

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Quick Facts
Patent No.
US 8,020,017
App. No.
12/192,683
Granted
Sep 13, 2011
Kind
B2
Abstract

A method of operating a circuit, including operating in a first mode, wherein in the first mode, a first power domain operates in an active power mode and a second power domain operates in an active power mode, wherein in the first mode, a first set of at least one terminal of a first circuit of the first power domain are coupled to a second set of at least one terminal of a second circuit of the second power mode via an isolation circuit for providing signals from the first circuit to the second circuit, is provided. The method further includes operating the circuit in a second mode, wherein in the second mode, the first power domain operates in a power gated mode and a second power domain operates in an active power mode.

Claims (44)

1. A circuit comprising:

a first power domain, the first power domain including a first set at least one terminal, the first set of at least one terminal configured for providing signals;

a second power domain, the second power domain including a second set of at least one terminal, the second set configured for receiving signals, the first power domain is power gatable with respect to the second power domain;

a controller circuit, the controller circuit having a third set of at least one terminal for providing programmable values; and

isolation circuitry having an input coupled to the first set of at least one terminal, a second input coupled to the third set of at least one terminal, and an output coupled to the second set of at least one terminal, the isolation circuitry including an input to receive an isolate signal, wherein the isolation circuit couples the first set of at least one terminal to the second set of at least one terminal to receive signals based on the isolation signal being in a first state and couples the third set of at least one terminal to the second set of at least one terminal to receive signals based on the isolation signal being at a second state.

2. The circuit of claim 1 , wherein when the first power domain is in a power gated mode and the second power domain is in an active mode, the isolation signal is the second state.

3. The circuit of claim 1 , wherein the first power domain includes a slave device, the first set of at least one terminal being a terminal of the slave device, the second power domain including a master device, the second set of terminals being a terminal of the master device.

4. The circuit of claim 3 , wherein the second set of at least one terminal is configurable to receive a response signal, wherein at least a portion the response signal is provided by the controller via the isolation circuit when the isolation signal is in the second state.

5. The circuit of claim 4 , wherein the response signal is a sequence of multi-bit values, wherein the at least a portion of the response signal provided by the controller has different values in the sequence.

6. The circuit of claim 1 , wherein:

the second power domain includes a fourth set of at least one terminal, the fourth set of at least one terminal configured to provide signals;

the first power domain includes a fifth set of at least one terminal coupled to the fourth set of at least one terminal, the fifth set of at least one terminal receiving an access signal from the second power domain via the fourth set of at least one terminal indicating that circuitry of the second power domain desires access to circuitry of the first power domain;

wherein the controller includes a sixth set of at least one terminal, the sixth set of at least one terminal coupled to the fourth set of at least one terminal to receive the access signal from the second power domain.

7. The circuit of claim 1 , wherein when the first power domain is in a power gated mode, the controller providing at least a portion of a response signal to the second set of at least one terminal via the isolation circuit in response to the controller receiving an access signal from circuitry of the second power domain.

8. The circuit of claim 1 , wherein the third set of at a least one set of terminals is configurable to provide a first value at a first time when the isolation signal is in second state and to provide a second value with the isolation signal at the second state at a second time.

9. A method of operating a circuit, the method comprising:

operating in a first mode, wherein in the first mode, a first power domain operates in an active power mode and a second power domain operates in an active power mode, wherein in the first mode, a first set of at least one terminal of a first circuit of the first power domain are coupled to a second set of at least one terminal of a second circuit of a second power mode via an isolation circuit for providing signals from the first circuit to the second circuit; and

operating in a second mode, wherein in the second mode, the first power domain operates in a power gated mode and a second power domain operates in an active power mode, wherein in the second mode, the second set of at least one terminal is coupled to a third set of at least one terminal via the isolation circuit, wherein the first set of at least one terminal is not coupled to the second set of at least one terminal via the isolation circuit,

wherein when operating in the first mode, the third set of at least one terminal is not coupled to the second set of at least one terminal via the isolation circuit, and

wherein when operating in the second mode, the third set of at least one terminal provides via the isolation circuit to the second set of at least one terminal a first value at a first time and a second value at a second time.

10. The method of claim 9 , wherein the third set of at least one terminals are terminals of a controller, the controller provides an isolation signal to the isolation circuit for coupling and decoupling the first set of at least one terminal to the second set of at least one terminal.

11. The method of claim 9 , wherein the third set of at least one terminal are a terminal of a controller, wherein when operating in the second mode, the controller monitors signals provided by the second circuit to determine when the second circuit is trying to access the first circuit, wherein the controller provides an indication signal to the second circuit via the third set of at least one terminal and the isolation circuit to the second circuit.

12. The method of claim 11 , wherein the indication signal indicates an error to the second circuit.

13. The method of claim 11 , wherein the indication signal indicates to the second circuit to retry the access to the first circuit.

14. The method of claim 11 , further comprising:

when operating in the second mode, monitoring signals provided by the second circuit to determine when the second circuit is trying to access the first circuit,

in response to the second circuit trying to access the first circuit, placing the first power domain in an active mode and then placing the isolation circuit in a mode to couple the first set of at least one terminal to the second set of at least one terminal and to decouple the third set of at least one terminal from the second set of at least one terminal.

15. The method of claim 9 further comprising:

when operating in the second mode, monitoring signals by a controller, signals provided by the second circuit to determine when the second circuit is trying to access the first circuit, and

providing by the controller, the first value followed by the second value at the third set of at least one terminal in response to the second circuit trying to access the first circuit to indicate an error.

16. The method of claim 9 further comprising:

transitioning from the second mode to the first mode, wherein the transitioning includes placing the first power domain in an active mode and then placing the isolation circuit in a mode to couple the first set of at least one terminal to the second set of at least one terminal and to decouple the third set of at least one terminal from the second set of at least one terminal.

17. The method of claim 9 further comprising:

transitioning from the first mode to the second mode, wherein the transitioning includes placing isolation circuitry in a mode to couple the third set of at least one terminal to the second set of at least one terminal and to decouple the first set of at least one terminal from the second set of at least one terminal and then to place the first power domain in a gated power mode.

18. A method of operating a circuit, the method comprising:

operating in a first mode, wherein in the first mode, a first power domain of the circuit operates in an active power mode and a second power domain of the circuit operates in an active power mode, wherein in the first mode, a first set of at least one terminal of a first circuit of the first power domain are coupled to a second set of at least one terminal of a second circuit of the second power domain via an isolation circuit for providing signal values from the first circuit to the second circuit;

transitioning from the first mode to a second mode, wherein the transitioning includes placing the isolation circuit in a mode to couple a third set of at least one terminal to the second set of at least one terminal and to decouple the first set of at least one terminal from the second set of at least one terminal and then placing the first power domain in a gated power mode;

operating in the second mode, wherein in the second mode, the first power domain operates in the gated power mode and a second power domain operates in an active power mode, wherein in the second mode, the second set of at least one terminal is coupled to the third set of at least one terminal via the isolation circuit, wherein the first set of at least one terminal is not coupled to the second set of at least one terminal via the isolation circuit;

wherein when operating in the first mode, the third set of at least one terminal is not coupled to the second set of at least one terminal via the isolation circuit;

wherein when operating in the second mode, providing by the third set of at least one terminal via the isolation circuit to the second set of at least one terminal a first value at a first time and a second value at a second time;

transitioning from the second mode to the first mode, wherein the transitioning includes placing the first power domain in an active mode and then placing the isolation circuit in a mode to couple the first set of at least one terminal to the second set of at least one terminal and to decouple the third set of at least one terminal from the second set of at least one terminal.

19. The method of claim 18 , wherein:

when operating in the second mode, monitoring signals provided by the second circuit to determine when the second circuit is trying to access the first circuit,

in response to the second circuit trying to access the first circuit, providing an indication signal to the second set of at least one terminal by the third set of at least one terminal via the isolation circuit.

Assignments (19)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0757 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Dec 9, 2008
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 021936/0772 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2008
From: PADHYE, MILIND P.; BAMFORD, NOAH W.; SINGHANIA, ANUJ
To: FREESCALE SEMICONDUCTOR, INC.
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