Self-calibrating data conversion circuitry and method therefor
View Patent ↗A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.
1. A data converter, comprising:
conversion circuitry for receiving an input and providing an uncalibrated conversion result;
calibration storage circuitry which stores a calibration value,
wherein the calibration value is produced by the data converter;
error determination circuitry, coupled to the conversion circuitry and to the calibration storage circuitry; and
result adjustment circuitry, coupled to the conversion circuitry and the calibration storage circuitry, said result adjustment circuitry using the calibration value to digitally adjust the uncalibrated conversion result to produce a calibrated conversion result, wherein the result adjustment circuitry comprises circuitry for performing a mathematical operation, and wherein the mathematical operation is equivalent to subtracting the calibration value from the uncalibrated conversion result to produce the calibrated conversion result, and wherein the calibrated conversion result corresponds to the input.
2. A data converter as in claim 1 , wherein the conversion circuitry comprises a charge redistribution array, a comparator, and SAR circuitry.
3. A data converter as in claim 2 , wherein the comparator is a differential comparator.
4. A data converter as in claim 2 , wherein the charge redistribution array comprises a plurality of capacitors.
5. A data converter as in claim 4 , wherein the plurality of capacitors in the charge redistribution array are sized so that errors between conversion bits are always positive.
6. A data converter as in claim 4 , wherein the plurality of capacitors in the charge redistribution array are sized so that there are no non-monotonicities in the uncalibrated conversion result after conversion.
7. A data converter as in claim 1 , wherein the result adjustment circuitry comprises an accumulator.
8. A data converter as in claim 1 , wherein the data converter comprises an analog to digital converter.
9. A data converter as in claim 1 , further comprising:
calibration control circuitry; and
a multiplexer having a first data input coupled to the calibration control circuitry, having a second data input coupled to the conversion circuitry, having a control input coupled to the calibration control circuitry, and having an output coupled to the conversion circuitry,
wherein the multiplexer provides data from the first data input to the conversion circuitry during a self-calibration process, and
wherein the multiplexer provides data from the second data input to the conversion circuitry during a conversion process.
10. A self-calibration method for providing a calibration value, the method comprising:
during a sample phase, sampling a first voltage on selected ones of a plurality of capacitors, sampling a second voltage on other selected ones of the plurality of capacitors, and charging inputs to a comparator to a common mode voltage;
releasing the inputs to the comparator;
during a compare phase, sampling the second voltage on the selected ones of the plurality of capacitors, sampling the first voltage on the other selected ones of the plurality of capacitors;
performing successive approximation on selected bits; and
storing a result of the successive approximation as a first calibration value corresponding to a first one of the plurality of capacitors.
11. A method as in claim 10 , wherein the method is repeated to produce a second calibration value corresponding to a second one of the plurality of capacitors.
12. A method as in claim 11 , wherein the first calibration value is added to an error value to produce the second calibration value.
13. A method, comprising:
executing a first portion of a self-calibration sequence in a data converter by performing steps [a], [b], and [c] in a sample phase of the data converter:
[a] charging a first terminal of a capacitive element to a first voltage;
[b] charging a first terminal of each lower significance capacitive elements to a second voltage; and
[c] charging inputs to a comparator to a third voltage;
releasing the inputs to the comparator;
executing a second portion of the self-calibration sequence in the data converter by performing steps [g] and [h] in a compare phase of the data converter:
[g] switching the first terminal of the capacitive element to the second voltage; and
[h] switching the first terminal of each lower significance capacitive elements to the first voltage;
performing successive approximation on one or more bits of the data converter to produce a calibration value;
storing the calibration value in calibration storage circuitry;
receiving a received input to be converted by the data converter;
performing a conversion sequence on the received input to produce an uncalibrated result; and
mathematically combining the uncalibrated result and the calibration value to produce a calibrated result corresponding to the received input.
14. A method as in claim 13 , wherein the first voltage is a first reference voltage, wherein the second voltage is a second reference voltage, and wherein the first reference voltage is lower than the second reference voltage.
15. A method as in claim 13 , wherein the steps of the first portion of the self-calibration sequence and the steps of the second portion of the self-calibration sequence are repeated for a second capacitive element in the data converter before said step of performing the conversion sequence on the received input.
16. A method as in claim 13 , wherein the step of performing the conversion sequence comprises sampling an input voltage on less than all of the capacitive elements in a DAC in the data converter.
17. A method as in claim 13 , wherein the step of performing the conversion sequence comprises performing successive approximation to a predetermined accuracy level, and wherein the predetermined accuracy level is less than a maximum accuracy level of the data converter.
18. A method as in claim 13 , wherein the step of mathematically combining the uncalibrated result and the calibration value to produce a calibrated result corresponding to the received input comprises digitally adjusting the uncalibrated result based on which DAC capacitive elements remained coupled to the second voltage during the conversion sequence.