Method of separating a structure in a semiconductor device
View Patent ↗Removing a portion of a structure in a semiconductor device to separate the structure. The structure has two portions of different heights. In one example, the structure is removed by forming a spacer over the lower portion adjacent to the sidewall of the higher portion. A second material is then formed on the structure outside of the spacer. The spacer is removed and the portion under the spacer is then removed to separate the structure at that location. In one embodiment, separate channel regions are implemented in the separated structures. In other embodiments, separate gate structures are implemented in the separated structures.
1. A method of forming a semiconductor device comprising:
forming a structure comprising a first portion and a second portion, the first portion having a first height and the second portion having a second height, the first height is greater than the second height, wherein the first portion and the second portion are contiguous;
forming a spacer adjacent a sidewall of the first portion and over a first top portion of the second portion, the spacer being of a first material;
forming a second material over a second top portion of the second portion of the structure after the forming the spacer, the first material is etch selective with respect to the second material;
exposing the first top portion of the second portion of the structure, wherein the exposing includes removing the spacer over the first top portion;
removing material of the structure at a location of the first top portion to separate the first portion from the second portion at the location of the first top portion.
2. The method of claim 1 wherein the structure is of a material that includes a monocrystalline semiconductor material.
3. The method of claim 1 wherein the structure is located over a layer of dielectric material, wherein the removing material of the structure exposes the layer of dielectric material.
4. The method of claim 1 wherein the structure is of a material that includes polycrystalline silicon.
5. The method of claim 1 wherein a first control gate is implemented in the first portion and a second control gate is implement in the second portion.
6. The method of claim 1 wherein the first material includes nitride and the second material includes oxide.
7. The method of claim 1 wherein the forming the second material includes epitaxially growing material from the second top portion of the second portion of the structure.
8. The method of claim 7 , further comprising oxidizing material of the epitaxially grown material over the second top portion of the second portion.
9. The method of claim 1 further comprising:
forming a dielectric layer over the structure including on the sidewall before the forming the spacer, wherein the spacer is formed on a sidewall of the dielectric layer on the sidewall of the first portion and on the dielectric layer on the first top portion.
10. The method of claim 1 wherein the removing the material of the structure at the location of the first top portion includes etching the material with an anisotropic etch.
11. The method of claim 1 further comprising:
forming a gate structure over the first portion and the second portion after the removing;
selectively growing a material to rejoin the first portion and the second portion at a location outside of the gate structure.
12. The method of claim 1 further comprising:
implementing a first floating gate structure in the first portion and implementing a second floating gate structure in the second portion.
13. The method of claim 1 wherein the structure is formed over a layer of charge storage material.
14. The method of claim 13 wherein the charge storage material includes silicon nanocrystals.
15. The method of claim 1 wherein the structure includes silicon and the forming the second material includes oxidizing the silicon.
16. The method of claim 1 wherein the structure includes silicon and the forming the second material includes epitaxially growing silicon.
17. The method of claim 1 further comprising:
forming a layer of gate material over the structure after the removing.
18. The method of claim 1 wherein a first channel region is implemented in first portion and a second channel region is implemented in the second portion.
19. The method of claim 1 wherein implementing at least a portion of a current electrode region in the first portion and the second portion.
20. A method of forming a structure of a transistor, the method comprising:
forming a semiconductor structure comprising a first portion and a second portion, the first portion having a first height and the second portion having a second height, the first height is greater than the second height, wherein the first portion and the second portion are contiguous;
removing portions of the structure between the first portion and the second portion;
forming a layer of gate material over the first portion and the second portion;
patterning the layer of gate material to form a gate structure over the first portion and the second portion;
selectively growing a material to rejoin the first portion and the second portion at a location outside of the gate structure;
implementing at least a portion of a current electrode region in a region of the material selectively grown;
wherein a first channel region is located along a sidewall of the first portion under the gate structure and a second channel region is located along a top surface of the second portion under the gate structure, the first channel region and the second channel region are coupled to the current electrode region.
21. A method of forming a transistor, the method comprising:
providing a dielectric layer over a substrate;
forming a structure over the dielectric layer, the structure comprising a first portion and a second portion, the first portion having a first height and the second portion having a second height, the first height is greater than the second height, wherein the first portion and the second portion are contiguous;
removing portions of the structure between the first portion and the second portion to form an opening;
forming a first current electrode region in the substrate;
forming a second current electrode region in the substrate;
wherein a channel region separates the first current electrode region from the second current electrode region, wherein the opening includes a portion located over the channel region;
implementing a first gate structure in the first portion;
implementing a second gate structure in the second portion.
22. The method of claim 21 further comprising:
forming a charge storage layer over the substrate, wherein the structure is formed over the charge storage layer.