IP Library Granted Patent US 7,981,730
Granted Patent B2
US 7,981,730 · App. 12/169,964 · Granted Jul 19, 2011

Integrated conformal shielding method and process using redistributed chip packaging

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Quick Facts
Patent No.
US 7,981,730
App. No.
12/169,964
Granted
Jul 19, 2011
Kind
B2
Abstract

An integrated conformal electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a plurality of modules ( 30 - 33 ) to a process carrier ( 1 ) using a double side adhesive tape ( 2 ), and then sequentially depositing an insulating layer ( 15 ) and a conductive shielding layer ( 16 ) before encapsulating the modules with a molding compound ( 17 ). After removing the adhesive tape ( 2 ) to expose a surface of the encapsulated modules, a multi-layer circuit substrate ( 100 ) is formed over the exposed surface, where the circuit substrate includes shielding via structures ( 101 - 112 ) that are aligned with and electrically connected to the conductive shielding layer ( 16 ), thereby encircling and shielding the circuit module(s).

Claims (37)

1. A method for making a package assembly with integrated conformal EMI shielding, comprising:

attaching a plurality of microelectronic devices to a releasable attachment device;

forming an insulating layer over the a plurality of microelectronic devices;

applying an embedded grounding frame on the insulating layer comprising one or more grounding elements that are positioned to surround each of the plurality of microelectronic devices;

forming a conductive layer over the insulating layer, thereby forming a shielding structure over each of the plurality of microelectronic devices that is insulated from the plurality of microelectronic devices by the insulating layer and that is electrically connected to the embedded grounding frame;

forming an encapsulation package over the conductive layer to encapsulate the plurality of microelectronic devices, the encapsulation package comprising a first surface that contacts the releasable attachment device;

removing the removable attachment device from the first surface of the encapsulation package to thereby expose the plurality of microelectronic devices at the first surface of the encapsulation package; and

forming a multi-layer circuit substrate on the first surface of the encapsulation package comprising a plurality of circuit substrate shielding via structures, each of which is in electrical contact with the embedded grounding frame and a corresponding shielding structure over a microelectronic device.

2. The method of claim 1 , where attaching the plurality of microelectronic devices to a releasable attachment device comprises applying a double-sided tape layer to attach the plurality of microelectronic devices to a process carrier.

3. The method of claim 1 , where attaching the plurality of microelectronic devices to a releasable attachment device comprises applying a glue layer to attach the plurality of microelectronic devices to a process carrier.

4. The method of claim 1 , where applying the embedded grounding frame comprises:

attaching an embedded grounding frame to the releasable attachment device prior to forming the insulating layer, where the grounding frame comprises one or more grounding elements surrounding each of the plurality of microelectronic devices; and

selectively etching a plurality of openings in the insulating layer to expose the one or more grounding elements surrounding each of the plurality of microelectronic devices prior to forming a conductive layer over the insulating layer so that the conductive layer makes electrical contact with the embedded grounding frame.

5. The method of claim 1 , where forming a conductive layer over the insulating layer comprises depositing a conductive layer by physical vapor deposition, chemical vapor deposition, atomic layer deposition, electrolytic plating, electroless plating, flame spray, conductive paint spray, vacuum metallization, pad printing, sputtering, evaporation, dispensing or spray coating.

6. The method of claim 1 , where each of the circuit substrate shielding via structures comprises a conductive layer, such as a micro via layer, a micro pad layer, a grounding pad, an embedded grounding frame, or a trace layer that is electrically connected to the shielding structure.

7. The method of claim 1 , further comprising singulating each of the plurality of microelectronic devices along with its corresponding shielding structure and circuit substrate shielding via structure by cutting through the encapsulation package and the multi-layer circuit substrate along cut lines that separate the plurality of microelectronic devices.

8. A method of forming packaged circuit modules comprising:

providing a package panel comprising a plurality of circuit devices that are each conformally covered by an insulating layer on which is formed a conductive grounding frame comprising one or more grounding elements and a conductive shielding layer electrically connected to the conductive grounding frame before forming an encapsulation package so as to expose the plurality of circuit devices at a bottom surface of the encapsulation package;

forming a circuit substrate on the bottom surface of the encapsulation package comprising a plurality of conductive shielding via structures, each of which is in electrical contact with the conductive grounding frame and conductive shielding layer formed over the plurality of circuit devices; and

singulating the package panel into separate packaged circuit modules, each of which comprises one or more circuit devices covered by part of the conductive shielding layer and one or more conductive shielding via structures.

9. The method of claim 8 , where providing a package panel comprises:

providing a process carrier;

releasably attaching the plurality of circuit devices to the process carrier with a double-sided tape layer or glue layer; and

forming the insulating layer over the plurality of circuit devices;

forming a conductive grounding frame on the insulating layer prior to forming the conductive shielding layer, where the conductive grounding frame comprises one or more grounding elements that are positioned to electrically connect the conductive shielding layer through one or more openings formed in the insulating layer to a corresponding conductive shielding via structure in the circuit substrate;

forming the conductive shielding layer over the insulating layer and in electrical contact with the conductive grounding frame; and

encapsulating the plurality of circuit devices with a mold encapsulant to form the encapsulation package.

10. The method of claim 9 , further comprising selectively etching a plurality of openings in the insulating layer after forming the encapsulation package and prior to forming the circuit substrate, thereby exposing the conductive grounding frame surrounding each of the plurality of circuit devices.

11. The method of claim 9 , where forming the conductive grounding frame comprises releasably attaching a conductive grounding frame to the process carrier to surround each of the plurality of circuit devices so that the conductive grounding frame is exposed at a bottom surface of the encapsulation package and positioned in alignment with the conductive shielding via structures.

12. The method of claim 11 , further comprising selectively etching a plurality of openings in the insulating layer to expose the conductive grounding frame surrounding each of the plurality of circuit devices prior to forming the conductive shielding layer over the insulating layer so that the conductive shielding layer makes electrical contact with the conductive grounding frame.

13. The method of claim 8 , where forming a circuit substrate comprises forming a multi-layer circuit substrate in which each of the plurality of conductive shielding via structures is substantially aligned with and electrically connected to the conductive shielding layer formed in the encapsulation package so as to surround and shield each of the plurality of circuit devices.

14. The method of claim 13 , where forming the multi-layer circuit substrate comprises forming conductive shielding via structures with one or more conductive layers in the multi-layer circuit substrate, such as a micro via layer, a micro pad layer, a grounding pad, an embedded grounding frame, or a trace layer that is electrically connected to the conductive shielding layer.

15. A high density RF module package comprising:

an encapsulant package formed to encapsulate one or more microelectronic circuits so as to expose the one or more microelectronic circuits at a bottom surface of the encapsulant package, where the one or more microelectronic circuits are covered with a conformal conductive shield coating formed internally to the encapsulant package to shield the one or more microelectronic circuits against electromagnetic interference; and

a circuit substrate formed on the bottom surface of the encapsulant package, where the encapsulant package comprises an embedded ground frame which is exposed at the bottom surface of the encapsulant package and positioned in alignment with the shielding via structure.

16. The high density RF module package of claim 15 , where the circuit substrate comprises a multi-layer circuit substrate comprising a shielding via structure that is electrically connected to the conformal conductive shield coating formed in the encapsulant package so that that the shielding via structure surrounds at least part of an area below the one or more microelectronic devices.

17. The high density RF module package of claim 16 , where the circuit substrate comprises a shielding via structure formed with one or more conductive layers in the circuit substrate, such as a micro via layer, a micro pad layer, a grounding pad, an embedded grounding frame, or a trace layer that is electrically connected to the conformal conductive shield coating.

Assignments (20)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0757 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 024085/0001 →