Provision of extended addressing modes in a single instruction multiple data (SIMD) data processor
View Patent ↗Executing a first memory access instruction with update by an N-bit processor includes accessing at least one source register of a plurality of registers, wherein the accessing includes accessing a first register, wherein each register of the plurality of registers includes a main portion of N bits and an extension portion of M bits, wherein the main portion of the first register includes a first address operand. The execution of the first instruction further includes forming a memory access address using the first address operand; using the memory access address as an address for a memory access; producing an updated address operand; and writing the updated address operand to the main portion of the first register. The producing includes accessing an extension portion of a source register of the at least one source register to obtain modifying information and using the modifying information in the producing an updated address operand.
1. A method of operating a data processing system, comprising:
executing a first instruction by an N-bit processor, wherein the first instruction is a memory access instruction with update, wherein the execution of the first instruction includes:
accessing at least one source register of a plurality of registers, wherein the accessing the at least one source register includes accessing a first register of the plurality of registers, wherein each register of the plurality of registers includes a main register portion of N bits and an extension register portion of M bits, wherein the main register portion of the first register includes a first address operand, wherein each of N and M are a positive integer;
forming a memory access address using the first address operand;
using the memory access address as an address for a memory access;
producing an updated address operand, wherein the updated address operand is based on the first address operand;
writing the updated address operand to the main portion of the first register;
wherein the producing includes accessing an extension portion of a source register of the at least one source register to obtain modifying information and using the modifying information in the producing an updated address operand.
2. The method of claim 1 wherein the accessing an extension portion of a source register of at least one source register to obtain modifying information includes accessing the extension register portion of the first register to obtain the modifying information.
3. The method of claim 2 wherein the first registers is a base register for the first instruction and the first address operand is a base address.
4. The method of claim 1 wherein:
the at least one source register includes an index register of the plurality of registers, wherein the accessing an extension portion of a source register of at least one source register to obtain modifying information includes accessing the extension register portion of the index register to obtain the modifying information.
5. The method of claim 1 wherein:
the first instruction is for accessing a memory operand stored in a circular buffer; and
the modifying information includes an indication of buffer length of the circular buffer.
6. The method of claim 5 wherein the modifying information includes an indication of a modulus of the circular buffer.
7. The method of claim 5 wherein the modifying information includes an indication of an offset value used in accessing the circular buffer.
8. The method of claim 1 wherein:
the first processor instruction when executed, performs a bit reverse incrementing operation;
the modifying information includes an indication of a mask value for the bit reverse incrementing operation.
9. The method of claim 1 wherein:
the executing a first instruction includes determining that an offset field of the first instruction indicates a first value;
the executing the first instruction includes accessing an extension portion of a source register of the at least one source register to obtain modifying information in response to the offset field indicating the first value;
wherein if an offset field of a memory access instruction with update does not indicate the first value, producing an updated address operand for a memory access instruction with update will not include using modifying information from an extension portion of a source register for the memory access instruction with update.
10. The method of claim 1 wherein the extension portions of the plurality of registers are not used when executing scalar integer instructions.
11. The method of claim 1 wherein the extension portions of the plurality of registers are provided for storing SIMD vector elements.
12. The method of claim 1 wherein the first instruction is a SIMD instruction.
13. The method of claim 1 wherein:
an extension portion of the source register of the at least one source register includes a mode field and a control field;
wherein the modifying information is located in the control field;
wherein the producing an updated address operand includes producing an updated address operand as per a plurality of updating techniques, wherein the mode field indicates which technique of the plurality is to be used in the producing.
14. The method of claim 1 further comprising:
executing a second instruction by the processor, wherein the second instruction is a memory access instruction with update, wherein the execution of the second instruction includes:
accessing the main register portion of the first register to obtain the updated address operand;
forming a second memory access address using the updated address operand;
using the second memory access address as an address for a second memory access.
15. The method of claim 1 wherein:
the forming the memory access address includes adding the first address operand with a first value to derive the memory access address;
the producing an updated address operand includes modifying the memory access address using the modifying information.
16. A processor comprising:
a plurality of registers, each of the plurality of registers includes a main portion and an extension portion, wherein the main portion is N-bits and the extension portion is M-bits, wherein the processor is an N-bit processor, wherein each of N and M is a positive integer;
an execution unit, the execution unit for executing instructions, wherein registers of the plurality of registers are utilized as source registers and destination registers in the execution of instructions by the execution unit;
wherein the execution unit accesses at least one source register of the plurality of registers for executing a first memory access instruction with update, wherein the execution unit uses modifying data from an extension portion of a source register of the at least one source registers to update a first address operand from a main portion of a first source register of the at least one source registers to produce an updated address operand, wherein the updated address operand is written to the main portion of the first source register.
17. The processor of claim 16 wherein the execution unit uses modifying data from an extension portion of the first source register to update the first address operand.
18. The processor of claim 16 wherein:
the first memory access instruction is for accessing a memory operand stored in a circular buffer;
the modifying information includes an indication of buffer length of the circular buffer.
19. The processor of claim 16 wherein:
the first memory access instruction when executed, performs a bit reverse incrementing operation;
the modifying information includes an indication of a mask value for the bit reverse incrementing operation.
20. The processor of claim 16 wherein:
the extension portions of the plurality of registers are not used when executing scalar integer instructions by the execution unit;
the extension portions of the plurality of registers are provided for storing SIMD vector elements.
21. The processor of claim 16 wherein M equals N.