Apparatus and method for providing a clock signal
View Patent ↗A clock circuit which may include a first clock input for receiving a first clock signal and a second clock input for receiving a second clock signal. A clock calibration unit is connected to the first clock input and the second clock input. The calibration unit may calibrate the second clock signal relative to the first clock signal. The clock calibration unit may have a calibration output for outputting a calibrated clock signal. The clock circuit may include a switch unit connected to the first clock input and the calibration output. The switch unit can select a selected clock signal selected from the first clock signal and the calibrated signal. The switch unit has a switch output for outputting the selected clock signal. A switch control unit is connected to the switch unit for controlling which signal is selected based on a selection criterion and a clock circuit output is connected to the switch unit for outputting the selected clock signal.
1. A clock circuit, including:
a first clock input for receiving a first clock signal;
a second clock input for receiving a second clock signal;
a clock calibration unit connected to said first clock input and said second clock input, for calibrating the second clock signal relative to said first clock signal, said clock calibration unit having a calibration output for outputting a calibrated clock signal;
a switch unit connected to said first clock input and said calibration output, for selecting a selected clock signal selected from said first clock signal and said calibrated clock signal, said switch unit having a switch output for outputting said selected clock signal;
a switch control unit connected to said switch unit for controlling which signal is selected based on at least one selection criterion;
a clock circuit output connected to said switch unit for outputting said selected clock signal.
2. A clock circuit as claimed in claim 1 , wherein said switch control unit includes a failure detection unit connected to said first clock input, for controlling said switch unit to select said calibrated clock signal when a failure in said first clock signal is detected.
3. A clock circuit as claimed in claim 2 , wherein said failure detection unit is arranged to detect whether a clock frequency of the first clock signal is within a predetermined range.
4. A clock circuit as claimed in claim 3 , wherein said range has an upper limit and/or a lower limit.
5. A clock circuit as claimed in claim 1 , wherein said calibration circuit is arranged to repeatedly calibrate the second clock signal to the first clock signal during a period of time said first clock signal is selected as said selected clock signal.
6. A clock circuit as claimed in claim 1 , wherein said calibration unit is arranged to calibrate the second clock signal with a frequency which is a multiple of a frequency of said first clock signal.
7. A clock circuit as claimed in claim 6 , wherein said calibration unit is arranged to output the calibrated clock signal with, within a suitable margin of error, the same frequency as the first clock signal.
8. A clock circuit as claimed in claim 1 , wherein said calibration unit is arranged to count a number of clock cycles of the second clock signal during a predetermined number of clock cycles of the first clock signal.
9. A clock circuit as claimed in claim 8 , wherein said calibration unit is arranged to output the calibrated clock signal with a period which is proportional to said counted number of clock cycles.
10. A clock circuit as claimed in claim 1 , wherein said calibration unit is connected to said switch control unit, for terminating said calibrating when said calibrated clock signal is selected as said selected clock signal; and wherein said calibration unit is arranged to output the calibrated clock signal based on a calibration performed prior to terminating said calibration.
11. A clock circuit as claimed in claim 1 , wherein said calibration unit is arranged to calibrate the second clock signal relative to a first state of the first clock signal and relative to a second state of the first clock signal.
12. A clock circuit as claimed in claim 1 , wherein said second clock input is connected to a local clock, said local clock having a clock frequency lower than a clock frequency of the first clock signal.
13. A clock circuit as claimed in claim 1 , wherein the first clock signal is a pulse width modulation clock signal.
14. A clock circuit as claimed in claim 1 , including a modulation circuit for modulating at least one of: the first clock signal, the second clock signal and the selected signal.
15. A clock circuit as claimed in claim 14 , wherein said modulation circuit is a pulse-width modulation circuit.
16. A system or network, including at least two clock circuits as claimed in claim 1 .
17. A system or network as claimed in claim 16 , including a first clock for providing said first clock signal and a clock control unit for inhibiting transmission of the first clock signal to said clock circuits after a predetermined period of time.
18. A system or network as claimed in claim 17 , wherein said clock control unit is arranged to enable transmission of said first clock signal to said clock circuits after a predetermined period of time, during which period of time said transmission has been inhibited.
19. A method for providing a clock signal, including;
receiving a first clock signal;
receiving a second clock signal;
calibrating the second clock signal relative to said first clock signal; and
outputting a calibrated clock signal;
selecting a selected clock signal selected from said first clock signal and said calibrated clock signal;
controlling which signal is selected based on at least one selection criterion;
outputting said selected clock signal.