IP Library Granted Patent US 7,821,103
Granted Patent B2
US 7,821,103 · App. 12/207,127 · Granted Oct 26, 2010

Counter-doped varactor structure and method

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Quick Facts
Patent No.
US 7,821,103
App. No.
12/207,127
Granted
Oct 26, 2010
Kind
B2
Abstract

An improved varactor diode ( 40 ) is obtained by providing a substrate ( 41 ) having a first surface ( 43 ), in which are formed a P+ region ( 53, 46 ) proximate the first surface ( 43 ), a first N region ( 54, 45 ) located beneath the P+ region ( 53, 46 ), an N well region ( 56, 44 ) located beneath the first N region ( 54, 45 ) and a first P counter-doped region ( 55 ) located between the first N region ( 54, 45 ) and the N well region ( 56, 44 ), thereby forming an P+NPN structure for the varactor diode. In some embodiments, a second P-type counter-doped region ( 59 ) is provided within the N-well region ( 56, 44 ) so as to reduce the N doping concentration within the N well region ( 56, 44 ) but without creating a further PN junction therein. The net doping profile ( 52 ) provides varactor diodes ( 40 ) having a larger tuning ratio than varactors ( 20 ) without such counter-doped regions. By interchanging N and P regions an N+PNP varactor is obtained.

Claims (36)

1. A varactor diode, comprising:

a substrate having a first surface;

a relatively highly doped first region of a first conductivity type and first peak dopant concentration in or on the substrate proximate the first surface;

a second region of a second, opposite conductivity type and second peak dopant concentration in the substrate located beneath the first region;

a third region of the second conductivity type and third peak dopant concentration located in the substrate beneath the second region; and

a fourth counter-doped region of the first conductivity type and fourth peak dopant concentration located between the second region and the third region, thereby forming a P+NPN or an N+PNP structure for the varactor diode.

2. The varactor diode of claim 1 , further comprising, a fifth counter-doped region of the first conductivity type within the third region thereby locally reducing net doping of the second conductivity type within a portion of the third region without creating a further PN or NP junction therein.

3. The varactor diode of claim 1 , further comprising a relatively highly doped fifth region of the second conductivity type ohmically coupled to the third region, thereby forming a P+NPNN+ or N+PNPP+ varactor.

4. The varactor diode of claim 1 , wherein the second peak dopant concentration is about equal to or larger than the fourth peak dopant concentration.

5. The varactor diode of claim 4 , wherein the second peak dopant concentration is about 1 to 100 times the fourth peak dopant concentration.

6. The varactor diode of claim 5 , wherein the second peak dopant concentration is about 1 to 10 times the fourth peak dopant concentration.

7. The varactor diode of claim 6 , wherein the second peak dopant concentration is about 2 to 6 times the fourth peak dopant concentration.

8. The varactor diode of claim 1 , wherein the fourth peak dopant concentration is about less than or equal to the third peak dopant concentration.

9. The varactor diode of claim 8 , wherein the fourth peak dopant concentration is about 0.01 to 1 times the third peak dopant concentration.

10. A method for forming a varactor diode, comprising:

providing a substrate having a first surface, then in any order;

forming a first region of a first conductivity type and first peak dopant concentration in or on the substrate proximate the first surface;

providing a second region of a second, opposite conductivity type and second peak dopant concentration in the substrate located beneath the first region;

forming a third region of the second conductivity type and third peak dopant concentration located in the substrate beneath the second region; and

providing a fourth counter-doped region of the first conductivity type and fourth peak dopant concentration located at a depth between a depth of the peak concentration of the second region and a depth of the peak concentration of the third region, thereby forming a P+NPN or N+PNP structure for the varactor diode.

11. The method of claim 9 , further comprising, forming a fifth counter-doped region of the first conductivity type within the third region thereby locally reducing net doping of the second conductivity type within a portion of the third region without creating a further PN or NP junction therein.

12. The method of claim 10 , wherein the first region forms a first PN or NP junction with the second region and the second region forms a second NP or PN junction with the fourth region and the first PN or NP junction is separated from the second NP or PN junction by about 0.05 to 0.5 micrometers.

13. The method of claim 12 , wherein the fourth region and the first PN or NP junction is separated from the second NP or PN junction by about 0.05 to 0.3 micrometers.

14. The method of claim 13 , wherein the fourth region and the first PN or NP junction is separated from the second NP or PN junction by about 0.1 to 0.2 micrometers.

15. The method of claim 10 , wherein the first region forms a first PN or NP junction with the second region and the second region forms a second NP or PN junction with the fourth region and the fourth region forms a third PN or NP junction with the third region, and the first PN or NP junction is separated from the second NP or PN junction by a first distance and the second NP or PN junction is separated from the third PN or NP junction by a second distance, and the first distance is equal to the second distance within a factor of about 1.0 to 1.5.

16. The method of claim 10 , wherein the first region is formed by epitaxial growth.

17. A varactor diode, comprising:

a substrate having a first surface;

a P+ region in or on the substrate proximate the first surface;

a first N region in the substrate located beneath the P+ region;

an N well region located in the substrate beneath the first N region; and

a first P type counter-doped region located between the first N region and the N well region, thereby forming a P+NPN structure for the varactor diode.

18. The varactor diode of claim 17 , further comprising a second counter doped region located within the N well region so as to reduce the net doping within a portion of the N well region without forming a further PN or NP junction therein.

19. The varactor diode of claim 17 , wherein a first PN junction is formed between the P+ region and the first N region and a second NP junction is formed between the first N region and the first P type counter doped region and a third PN junction is formed between the first P type counter doped region and the N well region.

20. The varactor diode of claim 19 , wherein the first and second PN or NP junctions are separated by a first distance and the second and third NP or PN junctions are separated by a second distance and the first and second distances are equal within a factor of about 1.5 or less.

21. The varactor diode of claim 17 , wherein N and P type conductivities are interchanged, so that P type becomes N type and N type becomes P type, thereby forming an N+PNP structure for the varactor diode.

Assignments (29)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
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From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
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RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
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To: NXP B.V.
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