Granted Patent B2

US 7,723,823 · App. 12/178,800 · Granted May 25, 2010

Abstract

Claims (35)

1. A lateral electrostatic discharge (ESD) protection device, comprising:

a semiconductor substrate of a first conductivity type and first doping level;

a semiconductor layer overlying the substrate, and of the first conductivity type and a second doping level and having an outer surface spaced a first distance from the substrate;

emitter and collector regions of a second, opposite, conductivity type, laterally spaced apart by a second distance, and having third doping level greater than the second doping level;

a well region of the first conductivity type in but not extending through the semiconductor layer and having a doping level higher than the second doping level but less than or equal to the third doping level, and extending laterally from the emitter region toward but separated from the collector region by a third distance; and

a buried layer of the second conductivity type and doping level higher than the third doping level Ohmically coupled to the emitter region, and without a further buried layer of the second conductivity type Ohmically coupled to the collector region.

2. The device of claim 1 , wherein the first conductivity type is N-type.

3. The device of claim 1 , wherein the buried layer Ohmically coupled to the emitter region has a lateral width substantially similar to a lateral width of the emitter region.

4. The device of claim 1 , wherein the well region has a depth from the exterior surface toward the substrate of about 30 to 60 percent of the first distance.

5. The device of claim 1 , wherein the third distance is about 0 to 50 percent of the second distance.

6. The device of claim 1 , wherein the third distance is in the range of about 0 to 3 micrometers.

7. The device of claim 1 , wherein a DC ESD trigger voltage Vt 1 DC and a transient ESD trigger voltage Vt 1 TR differ in magnitude by less than about 25 percent of Vt 1 TR .

8. The device of claim 1 , wherein the buried layer region underlies the emitter region.

9. The device of claim 1 , wherein the emitter region and the collector region extend substantially through the semiconductor layer.

10. A lateral bipolar electrostatic discharge (ESD) protection device having a trigger voltage Vt 1 , comprising:

a semiconductor (SC) substrate;

an overlying epitaxial SC layer;

emitter-collector regions in the SC layer, laterally spaced apart by a first distance;

a base region adjacent the emitter region in the epitaxial SC layer extending laterally toward and separated from the collector region by a base-collector spacing in the epitaxial layer, which base-collector spacing is chosen to set a predetermined ESD trigger voltage Vt 1 ; and

a buried layer region under the emitter region Ohmically coupled thereto, but without a comparable buried layer region under the collector region, thereby providing an asymmetrical structure whose DC trigger voltage (Vt 1 DC ) and transient trigger voltage (Vt 1 TR ) are approximately equal.

11. The device of claim 10 , wherein the buried layer region extends laterally under the emitter region.

12. The device of claim 10 , wherein the base-collector spacing is in the range of about 0 to 50 percent of the first distance.

13. The device of claim 10 , wherein the epitaxial SC layer has a first thickness and the base region extends to a first depth from an outer surface of the epitaxial SC layer, which first depth is about 30 to 60 percent of the first thickness.

14. The device of claim 10 , wherein the substrate has a first dopant concentration, the epitaxial layer has a second dopant concentration equal or less than the first dopant concentration and the base region has a third dopant concentration greater than the second dopant concentrations.

15. The device of claim 11 , wherein the buried layer region is more heavily doped than the emitter region.

16. A lateral electrostatic discharge (ESD) protection device, comprising:

a semiconductor substrate of a first conductivity type and first doping level;

a semiconductor layer overlying the substrate, and of the first conductivity type and a second doping level equal or less than the first doping level and having an outer surface spaced a first distance from the substrate;

emitter and collector regions of a second, opposite, conductivity type, laterally spaced apart by a second distance, and having third doping levels greater than the second doping level;

a well region of the first conductivity type in but not extending through the semiconductor layer and having a doping level higher than the second doping level and extending laterally from the emitter region toward but separated from the collector region by a third distance, wherein the third distance is in the range of about 0 to 3 micrometers; and

a buried layer of the second conductivity type and doping level higher than the third doping level Ohmically coupled to the emitter region and having a lateral width substantially similar to a lateral width of the emitter region, and without a further buried layer of the second conductivity type Ohmically coupled to the collector region, wherein a DC ESD trigger voltage Vt 1 DC and a transient ESD trigger voltage Vt 1 TR are within 25 percent of each other at any given spacing of the third distance.

17. The device of claim 16 , wherein the well region has a depth from the exterior surface toward the substrate of about 30 to 60 percent of the first distance.

18. The device of claim 17 , wherein the buried layer region underlies the emitter region.

19. The device of claim 18 , wherein the emitter region and the collector region extend substantially through the semiconductor layer.

20. The device of claim 19 , wherein the first conductivity type is N-type.

Assignments (31)