Method and Device for Exchanging Data Using a Virtual Fifo Data Structure
A method and a device for exchanging data. The method includes: requesting the processor, by the data transfer controller, to initiate a transfer of multiple data chunks from the second memory unit to the Virtual FIFO data structure, in response to a status of the virtual FIFO data structure; sending the data transfer controller, by the processor a request acknowledgment and an indication about a size of a group of data chunks to be transferred to the virtual FIFO data structure; updating the state of the virtual FIFO data structure; transferring, by the second level DMA controller, the group of data chunks from the second memory unit to the virtual FIFO data structure; sending, by the processor a DMA completion acknowledgment indicating that the group of data chunks was written to the virtual FIFO data structure; and transferring, by a first level DMA controller, a data chunk from the virtual FIFO data structure to the hardware FIFO memory unit.
1 . A device, comprising
a processor;
a hardware FIFO memory unit;
a first level DMA controller, a second level DMA controller, an first memory unit that stores at least one virtual FIFO data structure, wherein the first level DMA controller is coupled to the hardware FIFO memory unit and to the first memory unit and wherein the second level DMA controller is coupled to the first memory unit and to a second memory unit;
a data transfer controller, coupled to processor and to the first level DMA controller, wherein the data transfer controller initiates transfer of data chunks between the hardware FIFO memory unit and the virtual FIFO data structure and initiates transfers of multiple data chunks between the second memory unit and the virtual FIFO data structure;
wherein the processor is adapted to determine a size of a data block.
2 . The device according to claim 1 wherein the multiple data chunks comprise a data block.
3 . The device, according to claim 1 wherein the data transfer controller is adapted to request from the processor to manage a data transfer of multiple data chunks between the second memory unit and the virtual FIFO data structure, to receive an indication from the processor that the request was accepted as well as a indication of a size of a group of data chunks to be handled, and, in response to a state of at least the virtual FIFO data structure, request from the processor to manage a data transfer of other data chunks between the second memory unit and the virtual FIFO data structure.
4 . The device according to claim 3 wherein the processor is further adapted to send to the data transfer controller a group of data chunks transfer indication indicative that the group of data chunks was transferred between the second memory unit and the virtual FIFO data structure, wherein the processor is further adapted to send to the data transfer controller another group of data chunks transfer indication indicative that another group of data chunks was transferred between the second memory unit and the virtual FIFO data structure.
5 . The device according to claim 1 wherein the processor is adapted to receive requests to manage data transfers of multiple data chunks from multiple data transfer controllers.
6 . The device according to claim 5 wherein the processor is adapted to send multiple reception indications in an order that corresponds to an order of reception of the requests to manage data transfers of multiple data chunks.
7 . The device according to claim 1 wherein processor is adapted to indicate a size of the group of data chunks to be handled by the processor.
8 . The device according to claim 1 wherein the data transfer controller is adapted to look for a last data chunk indication within metadata associated with a data chunk and in response to determine that a data block was transferred.
9 . The device according to claim 1 wherein the first level DMA controller transfers data and metadata associated to the data over substantially the same lines.
10 . A method comprising:
transferring, by a first level DMA controller, a data chunk from a hardware FIFO memory unit to a virtual FIFO data structure;
transferring, by a second level DMA controller, a data block from the virtual FIFO data structure to a second memory unit;
wherein a data block comprises multiple data chunks;
determining, by a processor, a size of a data block;
instructing, by a data transfer controller, a first level DMA controller to initiate a transfer of the data chunk from the hardware FIFO memory unit to the virtual FIFO data structure in response to a state of the virtual FIFO data structure and to a state of the hardware FIFO memory unit;
requesting, by the data transfer controller, the processor to initiate a transfer of multiple data chunks from the virtual FIFO data structure to the second memory unit, in response to a status of the virtual FIFO data structure.
11 . The method according to claim 10 wherein the multiple data chunks comprise a data block.
12 . The method according to claim 10 further comprising monitoring the status of the virtual FIFO data structure, by the data transfer controller.
13 . The method according to claim 10 wherein the monitoring comprises looking for a last data chunk indication within metadata associated with a data chunk and in response determining that a data block was transferred.
14 . The method according to claim 10 wherein the transferring, by a first level DMA controller, data chunks comprises providing data and data chunks over substantially the same lines.
15 . The method according to claim 10 , wherein the method further comprises:
sending, by the processor a request acknowledgment and an indication about a size of a group of data chunks to be transferred from the virtual FIFO data structure;
updating the state of the virtual FIFO data structure and transferring, by the second level DMA controller, a group of data chunks from the virtual FIFO data structure to the second memory unit.
16 . The method according to claim 10 , further comprising looking for a last data chunk indication within metadata associated with a data chunk and in response determining that a data block was transferred.
17 . The method according to claim 10 , wherein the method comprises instructing, by multiple data transfer controllers, multiple first level DMA controllers to initiate multiple provisions of multiple data chunks from multiple hardware FIFO memory units in response to a state of at least one virtual FIFO data structure.
18 . A method comprising:
transferring, by the second level DMA controller, multiple data chunks from the second memory unit to the virtual FIFO data structure;
transferring, by a first level DMA controller, a data chunk from the virtual FIFO data structure to the hardware FIFO memory unit;
requesting, by the data transfer controller, the processor to initiate a transfer of multiple data chunks from the second memory unit to the Virtual FIFO data structure, in response to a status of the virtual FIFO data structure and instructing, by a data transfer controller, a first level DMA controller to initiate a transfer of a data chunk from the virtual FIFO data structure to the hardware FIFO memory unit in response to a state of the hardware FIFO memory unit.
19 . The method according to claim 18 further comprising:
sending, by the processor, a request acknowledgment and an indication about a size of a group of data chunks to be transferred to the virtual FIFO data structure;
updating the state of the virtual FIFO data structure; and
sending, by the processor a DMA completion acknowledgment indicating that the group of data chunks was written to the virtual FIFO data structure.
20 . The method according to claim 18 further comprising looking for a last data chunk indication within metadata associated with a data chunk and in response determining that a data block was transferred.
21 . The method according to claim 18 wherein the multiple data chunks comprise a data block.