Method for generating a output clock signal having a output cycle and a device having a clock signal generating capabilities
View Patent ↗A device and a method for generating a output clock signal having a output cycle, the method includes: (i) adjusting a delay of an adjustable ring oscillator to provide a high frequency clock signal having a short cycle so that the output cycle substantially equals a sum of integer multiples of a sleep cycle and integer multiplies of the short cycle; wherein the output cycle differs from any integer multiples of the sleep cycle; wherein the sleep cycle characterizes a sleep clock signal that is generated by a low frequency sleep clock; wherein the short cycle is shorter than the sleep cycle; (ii) counting short cycles and sleep cycles; and (iii) generating, during a sleep mode, in response to the counting and to a predefined counting pattern, the first clock signal; wherein the generating includes activating the adjustable ring oscillator only during a portion of a single sleep cycle per each output cycle.
1. A method for generating an output clock signal having an output cycle, the method comprises:
adjusting a delay of an adjustable ring oscillator to provide a high frequency clock signal having a short cycle so that the output cycle substantially equals a sum of integer multiples of a sleep cycle and integer multiplies of the short cycle;
wherein the output cycle differs from any integer multiples of the sleep cycle;
wherein the sleep cycle characterizes a sleep clock signal that is generated by a low frequency sleep clock;
wherein the short cycle is shorter then the sleep cycle;
counting short cycles and sleep cycles; and
generating, during a sleep mode, in response to the counting and to a predefined counting pattern, the output clock signal;
wherein the generating comprises activating the adjustable ring oscillator only during a portion of a single sleep cycle per each output cycle.
2. The method according to claim 1 wherein the adjusting comprises adjusting a length of a chain of inverters of the adjustable ring oscillator that generates the high frequency clock signal.
3. The method according to claim 1 comprising:
determining or receiving the predefined counting pattern;
wherein the predefined counting pattern comprises multiple pairs of integers;
wherein at least two pairs of integers differ from each other;
wherein each pair of integers comprises a sleep clock integer and a second clock integer;
wherein the output cycle substantially equals a sleep clock integer of sleep cycles plus a second clock integer of short cycles.
4. The method according to claim 1 comprising determining or receiving the predefined counting pattern that comprises only a single pair of integers; wherein the single pair of integers comprises a sleep clock integer and a second clock integer; wherein the output cycle substantially equals a sleep clock integer of sleep cycles plus a second clock integer of short cycles.
5. The method according to claim 1 comprising adjusting the delay of the adjustable ring oscillator each output cycle.
6. The method according to claim 1 comprising adjusting the delay of the adjustable ring oscillator each group of output cycles.
7. The method according to claim 1 comprising adjusting the delay of the adjustable ring oscillator each output cycle in order to prevent a timing gap to exceed a timing threshold;
wherein the timing gap is a difference between a output cycle and a cycle obtained by counting sleep cycles and short cycles.
8. The method according to claim 1 comprising adjusting the delay of the adjustable ring oscillator during a manufacturing process of an integrated circuit that comprises the sleep clock and the adjustable ring oscillator.
9. The method according to claim 1 comprising adjusting the delay of the adjustable ring oscillator in response to a predefined change of a temperature or of a humidity level.
10. The method according to claim 1 comprising activating the adjustable ring oscillator in response to a drift of the at least the sleep cycle.
11. A device having a clock signal generating capabilities, the device comprises:
an adjustable ring oscillator adapted to generate a high frequency clock signal;
wherein a short cycle of the high frequency clock signal is responsive to an adjustable delay of the adjustable ring oscillator;
a controller, adapted to control an adjustment of the delay of the adjustable ring so that the output cycle substantially equals a sum of integer multiples of a sleep cycle and integer multiplies of the short cycle;
wherein the output cycle differs from any integer multiples of the sleep cycle;
wherein the sleep cycle characterizes a sleep clock signal that is generated by a low frequency sleep clock;
wherein the short cycle is shorter then the sleep cycle;
a counting circuit adapted to receive the sleep clock signal and the high frequency clock signal, count short cycles and sleep cycles and generate, during a sleep mode, and in response to a predefined counting pattern, the output clock signal;
wherein the adjustable ring oscillator is activated only during a portion of a single sleep cycle per each output cycle.
12. The device according to claim 11 wherein the adjustable ring oscillator comprises a chain of inverters having an adjustable length and wherein the adjustable delay is responsive to the length of the chain of inverters.
13. The device according to claim 11 wherein:
the counting circuit receives the predefined counting pattern;
the predefined counting pattern comprises multiple pairs of integers;
at least two pairs of integers differ from each other;
each pair of integers comprises a sleep clock integer and a second clock integer;
the output cycle substantially equals a sleep clock integer of sleep cycles plus a second clock integer of short cycles.
14. The device according to claim 11 wherein:
the counting circuit receives the predefined counting pattern that comprises only a single pair of integers;
the single pair of integers comprises a sleep clock integer and a second clock integer;
the output cycle substantially equals a sleep clock integer of sleep cycles plus a second clock integer of short cycles.
15. The device according to claim 11 wherein the adjustable ring oscillator adjusts the delay of the adjustable ring oscillator each output cycle.
16. The device according to claim 11 wherein the adjustable ring oscillator adjusts the delay of the adjustable ring oscillator each group of output cycles.
17. The device according to claim 11 wherein:
the adjustable ring oscillator adjusts the delay of the adjustable ring oscillator each in order to prevent a timing gap to exceed a timing threshold;
the timing gap is a difference between the output cycle and a cycle obtained by the counting.
18. The device according to claim 11 wherein the adjustable ring oscillator adjusts the delay of the adjustable ring oscillator during manufacturing process of an integrated circuit that comprises the sleep clock and the adjustable ring oscillator.
19. The device according to claim 11 wherein the adjustable ring oscillator adjusts the delay of the adjustable ring oscillator in response to a predefined change of a temperature or of a humidity level.
20. The device according to claim 11 wherein the adjustable ring oscillator adjusts the delay of the adjustable ring oscillator in response to a drift of the at least the sleep cycle.