System and method for providing external power on a universal serial bus
View Patent ↗A universal serial bus power control circuit including at least one first switch which selectively couples a power source node to an external power node, a comparator which detects when the external power node is charged, a feedback node for enabling voltage regulation, a charge circuit and a controller. The charge circuit charges the external power node from the power source node and selectively couples the feedback node to at least one of the power source node and the external power node. The controller opens the first switch when the external power node is not charged, controls the charge circuit to charge the external power node while coupling the feedback node to the power source node, and closes the first switch and couples the feedback node to the external power node in a host mode when the external power node is charged.
1. A universal serial bus power control circuit, comprising:
at least one first switch which selectively couples a power source node to an external power node when each of said at least one first switch is closed;
a comparator which detects when said external power node is charged;
a feedback node for enabling voltage regulation;
a charge circuit which charges said external power node from said power source node, and which selectively couples said feedback node to at least one of said power source node and said external power node; and
a controller which opens at least one of said at least one first switch when said external power node is not charged, which controls said charge circuit to charge said external power node while coupling said feedback node to said power source node, and which closes each of said at least one first switch and couples said feedback node to said external power node in a host mode when said external power node is charged.
2. The universal serial bus power control circuit of claim 1 , wherein said charge circuit comprises:
a second switch with a first resistance which selectively couples said power source node to said feedback node when closed;
a third switch with a second resistance which selectively couples said feedback node to said external power node when closed, wherein said second resistance is significantly greater than said first resistance; and
wherein during an off mode said controller closes said second switch and opens said third switch, wherein during a charge mode said controller closes both of said second and third switches to enable charging of said external power node, and wherein during said host mode said controller opens said second switch and closes said third switch.
3. The universal serial bus power control circuit of claim 1 , wherein said charge circuit comprises:
a second switch coupled between said power source node and said feedback node;
a third switch coupled between said feedback node and said external power node;
a controlled current source coupled between said power source node and said external power node; and
wherein during an off mode said controller turns off said controlled current source, closes said second switch and opens said third switch, wherein during a charge mode said controller turns on said controlled current source, closes said second switch and opens said third switch, and wherein during said host mode said controller turns off said controlled current source, opens said second switch and closes said third switch.
4. The universal serial bus power control circuit of claim 1 , wherein said comparator compares voltage of said external power node with a predetermined minimum voltage level.
5. The universal serial bus power control circuit of claim 1 , wherein said at least one first switch comprises:
a first switch which selectively couples said power source node to an internal power node when closed;
a second switch which selectively couples said internal power node to said external power node when closed; and
wherein said controller opens at least one of said first and second switches when not in said host mode and which closes both of said first and second switches in said host mode and when said external power node is charged.
6. The universal serial bus power control circuit of claim 3 , wherein said controlled current source comprises a fourth switch coupled in series with a resistance.
7. A method of providing external power on a universal serial bus, comprising:
coupling a feedback node to an internal source node when in an off mode and when in a charge mode;
charging an external power node from the internal source node when in the charge mode; and
when the external power node is charged, entering a host mode by coupling the internal source node to the external power node, coupling the feedback node to the external power node and decoupling the feedback node from the internal source node.
8. The method of claim 7 , wherein said charging the external power node comprises coupling a charge path from the internal source node to an external power node and decoupling the charge path when not in the charge mode.
9. The method of claim 7 , wherein said charging the external power node comprises activating a current source.
10. The method of claim 7 , wherein said charging the external power node comprises coupling a charge resistor between the internal source node and the external power node.
11. The method of claim 7 , wherein said coupling the internal source node to the external power node comprises closing each of at least one first switch coupled between the internal source node to the external power node.
12. The method of claim 7 , wherein:
said coupling a feedback node to the internal source node comprises closing a first switch with a first resistance provided between the feedback node and the internal source node;
wherein said coupling the feedback node to the external power node comprises closing a second switch with a second resistance provided between the feedback node and the external power node, wherein the second resistance is significantly greater than the first resistance;
wherein said charging the external power node from the internal source node comprises closing both of the first and second switches; and
wherein said decoupling the feedback node from the internal source node comprises opening the first switch.
13. The method of claim 7 , wherein:
said coupling the internal source node to the external power node comprises closing each of at least one first switch coupled in series between the internal source node and the external power node;
wherein said coupling a feedback node to the internal source node comprises closing a second switch provided between the feedback node and the internal source node;
wherein said decoupling the feedback node from the internal source node comprises opening the second switch;
wherein said coupling the feedback node to the external power node comprises closing a third switch provided between the feedback node and the external power node; and
wherein said charging an external power node comprises activating a current path provided between the internal source node and the external power node.
14. The method of claim 12 , wherein said coupling the internal source node to the external power node comprises closing each of at least one third switch provided between the internal source node and the external power node.
15. An electronic device, comprising:
an internal feedback node;
a regulator which provides source voltage on an internal source node, wherein said regulator has an internal feedback input coupled to said internal feedback node for regulating voltage level;
an external power node; and
a universal serial bus power control circuit, comprising:
at least one first switch which selectively couples said internal source node to said external power node when closed;
a charge circuit which charges said external power node from said internal source node, and which selectively couples said internal feedback node to at least one of said internal source node and said external power node;
a comparator which detects when said external power node is charged; and
a controller which opens said at least one first switch when said external power node is not charged, which controls said charge circuit to charge said external power node while coupling said internal feedback node to said internal source node, and which closes said at least one first switch and couples said internal feedback node to said external power node in a host mode when said external power node is charged.
16. The electronic device of claim 15 , wherein said charge circuit comprises:
a second switch with a first resistance which selectively couples said internal source node to said internal feedback node when closed;
a third switch with a second resistance which selectively couples said internal feedback node to said external power node when closed, wherein said second resistance is significantly greater than said first resistance; and
wherein during an off mode said controller closes said second switch and opens said third switch, wherein during a charge mode said controller closes both of said second and third switches, and wherein during said host mode said controller opens said second switch and closes said third switch.
17. The electronic device of claim 15 , wherein said charge circuit comprises:
a controlled current path coupled between said internal source node and said external power node; and
a controlled switch circuit coupled to said internal feedback node and coupled between said internal source node and said external power node.
18. The electronic device of claim 15 , further comprising:
an internal power node;
a universal serial bus internal regulator coupled to said internal power node; and
wherein said at least one first switch comprises:
a first switch coupled between said internal source node and said internal power node; and
a second switch coupled between said internal power node and said external power node.
19. The electronic device of claim 15 , wherein said universal serial bus power control circuit is compliant with USB OTG.
20. The electronic device of claim 17 , wherein said controlled current path comprises a switched charge resistance.