IP Library Granted Patent US 7,395,401
Granted Patent B2
US 7,395,401 · App. 11/241,299 · Granted Jul 1, 2008

System and methods for accessing solid-state memory devices

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,395,401
App. No.
11/241,299
Granted
Jul 1, 2008
Kind
B2
Abstract

The disclosure is directed to a method of determining memory parameters of a memory device. The method includes determining a communication protocol associated with the memory device, determining a page size of the memory device by using the communication protocol to communicate a page of data, determining a block size of the memory device by using the communication protocol to erase a block of the memory device, and determining a capacity of the memory device by using the communication protocol to determine a number of significant address bits.

Claims (60)

1. A method of determining memory parameters of a memory device, the method comprising:

determining a communication protocol associated with the memory device;

determining a page size of the memory device by using the communication protocol to communicate a page of data;

determining a block size of the memory device by using the communication protocol to erase a block of the memory device; and

determining a capacity of the memory device by using the communication protocol to determine a number of significant address bits.

2. The method of claim 1 , further comprising setting a descriptor associated with the memory device based on the page size, the block size, and the number of significant address bits.

3. The method of claim 2 , further comprising communicating with the memory device based on the descriptor.

4. The method of claim 1 , wherein determining the page size of the memory device includes:

selecting a particular page size;

writing test data to the memory device to a page location, the test data having a size equal to the particular page size;

reading results data from the memory device from the page location; and

determining whether the results data matches the test data.

5. The method of claim 4 , wherein a page location is the first page of the memory device.

6. The method of claim 1 , wherein determining the block size of the memory device includes:

writing test data to a storage device starting at a particular block, the test data having a selected size;

sending a command to the storage device to erase the particular block; and

reading data from the storage device starting at the particular block to locate unerased data.

7. The method of claim 1 , wherein determining the capacity of the memory device includes:

selecting an address, the address including a set of column bits and a set of row bits;

determining whether a location indicated by the address is available; and

changing the address by incrementally shifting a row bit of the set of row bits in response to determining that the location is available.

8. The method of claim 7 , further comprising setting the number of significant address bits in response to determining that the location is unavailable.

9. The method of claim 7 , wherein determining whether the location indicated by the address is available includes:

writing test data to the memory device at the address of the location;

reading results data from the memory device from the address of the location; and

comparing the test data to the results data.

10. The method of claim 1 , wherein determining the communication protocol includes sending a command to the memory device and determining whether an error occurs.

11. The method of claim 1 , further including accessing the memory device to determine a manufacture identification and a device identification.

12. A method of performing data storage, the method comprising:

selecting a first page size;

writing test data to a storage device to a page location, the test data having the first page size;

reading results data from the storage device from the page location; and

determining whether the results data is correct.

13. The method of claim 12 , wherein determining whether the results data is correct includes comparing the results data and the test data.

14. The method of claim 12 , wherein the test data is patterned data.

15. The method of claim 14 , wherein the patterned data is a list of primes.

16. The method of claim 12 , further comprising selecting a second page size when the results data is correct.

17. The method of claim 12 , further comprising setting a page size descriptor based on a smallest error free page size when the read data is incorrect.

18. The method of claim 12 , wherein the page location is a first page location.

19. A method of performing data storage, the method comprising:

writing test data to a storage device starting at a particular block, the test data having a selected size;

sending a command to the storage device to erase the particular block of data;

reading data from the storage device starting at the particular block of data to determine a location of unerased data; and

determining a block size of the storage device based on the location of unerased data.

20. The method of claim 19 , further comprising setting the block size of a storage device descriptor based on the location of the unerased data.

21. The method of claim 19 , wherein writing the test data to the storage device includes writing the test data to consecutive pages of the storage device beginning with a first page of the storage device.

22. The method of claim 19 , wherein reading data from the storage device includes reading data from consecutive pages of the storage device beginning with a first page of the storage device.

23. A method of performing data storage, the method comprising:

selecting an address, the address including a set of column bits and a set of row bits;

determining whether a location indicated by the address is accessible; and

changing the address by incrementally shifting a row bit of the set of row bits in response to determining that the location is accessible.

24. The method of claim 23 , further comprising setting the number of significant address bits in response to determining that the location indicated by the address is inaccessible.

25. The method of claim 24 , wherein setting the number of significant address bits includes setting the number of significant address bits based on the row bit used to determine the highest accessible location.

26. The method of claim 23 , wherein determining whether the location is accessible includes:

writing test data to the memory device at the address;

reading results data from the memory device from the address; and

comparing the test data to the results data.

27. A controller comprising:

a memory device descriptor; and

a device driver configured to access a memory device to determine a command protocol of the memory device, the device driver configured to use the command protocol to write data to the memory device to determine a page size, a block size, and an address space associated with the memory device, the device driver configured to manipulate the memory device descriptor based on the page size, the block size, and the address space and to communicate with the memory device based on the memory device descriptor.

Assignments (18)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
PATENT RELEASE Recorded Aug 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039707/0471 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 037354 FRAME: 0773. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT RELEASE. Recorded Aug 15, 2016
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, LLC
Reel/Frame 039723/0777 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2016
From: SIGMATEL, LLC
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037583/0428 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0757 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0734 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0773 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037355/0838 →
CHANGE OF NAME Recorded Nov 23, 2015
From: SIGMATEL INC.
To: SIGMATEL, LLC
Reel/Frame 037152/0127 →
SECURITY AGREEMENT Recorded Nov 12, 2013
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031626/0218 →