System and method for unified cache access using sequential instruction information
View Patent ↗Techniques for accessing a unified cache to obtain instruction information are provided. One exemplary technique includes accessing, during a first instruction access, a first cache line of a first way of a unified cache having a plurality of ways to obtain instruction information associated with a first instruction, enabling the first way and disabling one or more of the remaining ways of the unified cache in response to a determination that the first cache line comprises instruction information associated with a second instruction, and accessing, during a second instruction access, the first cache line of the first way to obtain instruction information associated with the second instruction.
1. A method comprising:
accessing, during a first instruction access, a first cache line of a first way of a unified cache having a plurality of ways to obtain instruction information associated with a first instruction;
in response to the first cache line comprising instruction information associated with a second instruction:
enabling the first way for a second instruction access; and
disable one or more of the remaining ways of the unified cache for the second instruction access by at least one of clock gating the one or more of the remaining ways or reducing power supplied to the one or more of the remaining ways; and
accessing, during the second instruction access, the first cache line of the first way to obtain instruction information associated with the second instruction.
2. The method of claim 1 , further comprising:
disabling a cache tag array of the unified cache in response to the first cache line comprising instruction information associated with the second instruction.
3. The method of claim 1 , further comprising:
accessing the unified cache for one or more data accesses between the first instruction access and the second instruction access, wherein the plurality of ways of the cache are enabled during the one or more data accesses.
4. The method of claim 1 , wherein enabling the first way and disabling one or more of the remaining ways is further in response to a determination that a state flag is asserted.
5. The method of claim 4 , wherein the state flag is maintained during one or more data accesses.
6. The method of claim 4 , further comprising:
clearing the state flag in response to a cache maintenance operation.
7. The method of claim 4 , further comprising:
clearing the state flag when the instruction information associated with the second instruction comprises the last data of the first cache line.
8. A system comprising:
a unified cache comprising a tag array and a data array, the data array comprising a plurality of ways, each way comprising a plurality of cache lines;
a cache controller coupled to the tag array and data array, wherein the cache controller is operable to:
access, during a first instruction access, a first cache line of a first way of the unified cache to obtain instruction information associated with a first instruction;
in response to the first cache line comprising instruction information associated with a second instruction:
enable the first way for a second instruction access; and
disable one or more of the remaining ways of the unified cache for the second instruction access by reducing power supplied to the one or more of the remaining ways; and
access, during the second instruction access, the first cache line of the first way to obtain instruction information associated with the second instruction.
9. The system of claim 8 , wherein the cache controller further is operable to:
disable a cache tag array of the unified cache in response to the first cache line comprising instruction information associated with the second instruction.
10. The system of claim 8 , wherein the cache controller is operable to enable the first way and disable one or more of the remaining ways further in response to a determination that a state flag is asserted.
11. The system of claim 10 , wherein the state flag is maintained during one or more data accesses.
12. The system of claim 10 , wherein the cache controller further is operable to:
clear the state flag in response to a cache maintenance operation.
13. The system of claim 10 , wherein the cache controller further is operable to:
clear the state flag when the instruction information associated with the second instruction comprises the last data of the first cache line.
14. A system comprising:
a unified cache comprising a tag array and a data array, the data array comprising a plurality of ways, each way comprising a plurality of cache lines;
a cache controller coupled to the tag array and data array, wherein the cache controller is operable to:
access, during a first instruction access, a first cache line of a first way of the unified cache to obtain instruction information associated with a first instruction;
in response to the first cache line comprising instruction information associated with a second instruction:
enable the first way for a second instruction access; and
disable one or more of the remaining ways of the unified cache for the second instruction access by clock gating the one or more of the remaining ways; and
access, during the second instruction access, the first cache line of the first way to obtain instruction information associated with the second instruction.
15. The system of claim 14 , wherein the cache controller further is operable to:
disable a cache tag array of the unified cache in response to the first cache line comprising instruction information associated with the second instruction.
16. The system of claim 14 , wherein the cache controller is operable to enable the first way and disable one or more of the remaining ways further in response to a determination that a state flag is asserted.
17. The system of claim 16 , wherein the state flag is maintained during one or more data accesses.
18. The system of claim 16 , wherein the cache controller further is operable to:
clear the state flag in response to a cache maintenance operation.
19. The system of claim 16 , wherein the cache controller further is operable to:
clear the state flag when the instruction information associated with the second instruction comprises the last data of the first cache line.