Apparatus for detecting clock failure and method therefor
View Patent ↗A clock failure detection circuit comprises clock failure detection logic having a clock input providing an input clock signal, a counter and a reference clock input providing a reference clock signal to the counter for counting a number of reference clock cycles. The counter comprises a reset input arranged to receive successive reset pulses generated by at least one clock edge of the input clock signal to reset a counter value of the counter. The counter value before reset is used to identify a clock frequency error. A method of detecting a clock failure is also described. By using a counter value based on the reference clock cycles, and a reset trigger based on a clock edge of the input signal, it is possible to identify a clock frequency error in a much shorter time.
1. A clock failure detection circuit comprises:
clock failure detection logic comprising a clock input, reset logic, and a counter, the clock input to receive an input clock signal;
the counter comprising a reference clock input to receive a reference clock signal, the counter to count a number of cycles of the reference clock, the counter is coupled to the reset logic arranged to generate a successive reset pulse in each duty cycle of the input clock signal based on at least one clock edge of each duty cycle of the input clock signal, and each successive reset pulse to reset a counter value of the counter, wherein the counter value before reset is used to allow a clock frequency error within a single clock period of the input clock signal to be identified.
2. The clock failure detection circuit of claim 1 , wherein the clock failure detection logic is further arranged to identify whether the clock frequency error is outside of a clock operation range, wherein the clock operation range includes a higher limit of a clock frequency error, a lower limit of the clock frequency error, or both the higher limit and the lower limit.
3. The clock failure detection circuit of claim 1 , wherein the counter comprises at least one output to provide an error signal in response to the counter reaches a value between successive reset pulses outside of a counter range representative of the clock operation range.
4. The clock failure detection circuit of claim 1 , wherein the counter comprises two outputs, wherein a first output is to provide an error signal in response to a high frequency clock error limit being activated based upon the counter failing to reach a minimum value between successive reset pulses, and a second output is to provide an error signal in response to a low frequency clock error limit being activated based upon the counter exceeding a maximum value between successive reset pulses.
5. The clock failure detection circuit of claim 1 , wherein the counter is further coupled to at least one latch arranged to latch a clock error signal in response to an enable signal generated by enable logic coupled to the at least one latch.
6. The clock failure detection circuit of claim 5 wherein the clock error signal, generated in response to a low frequency clock error limit being exceeded, latches an error bit from the at least one latch.
7. The clock failure detection circuit of claim 1 wherein the clock failure detection logic comprises a first NAND logic gate to receive the input clock signal and a first delay element to receive the input clock signal, such that an output signal of the first delay element is provided to a second inverted input of the first NAND logic gate, and an output of the first NAND logic gate is to provide an enable pulse to latch a clock error signal from the counter.
8. The clock failure detection circuit of claim 7 wherein the enable pulse comprises a pulse width equal to the first delay.
9. The clock failure detection circuit of claim 7 wherein the clock failure detection logic comprises a second NAND logic gate coupled to a second delay element such that the output signal of the first delay element is provided to a first input of the second NAND logic gate.
10. The clock failure detection circuit of claim 9 wherein an output signal of the second delay element is to be provided to a second inverted input of the second NAND logic gate, and an output of the second NAND logic gate is to provide a reset pulse for resetting the counter.
11. The clock failure detection circuit of claim 10 wherein the reset pulse comprises a pulse width equal to a delay of the second delay element.
12. The clock failure detection circuit of claim 7 wherein the clock failure detection logic is arranged to generate an enable pulse, a reset pulse, or both an enable pulse and a reset pulse upon each rising and trailing edge of the input clock signal.
13. The clock failure detection circuit of claim 7 wherein the clock failure detection logic comprises a comparator that is arranged to compare time periods between successive enable pulses or reset pulses to identify whether a clock failure is in response to a misaligned clock duty cycle.
14. A method of detecting a clock failure comprising:
providing an input clock signal;
providing a reference clock signal to a counter;
counting a number of reference clock cycles of the reference clock signal;
generating a successive reset pulse in each corresponding duty cycle of the input clock signal using at least one clock edge of the input clock signal;
receiving the successive reset pulses at the counter to reset a counter value; and
identifying a clock frequency error within a single clock period of the input clock signal based on the counter value before reset.
15. The method of claim 14 further comprising:
identifying whether the clock frequency error is outside of a clock operation range wherein the clock operation range includes a higher limit of a clock frequency error and a lower limit of the input clock frequency error.
16. The method of claim 14 further comprising:
providing an error signal, in response to the counter reaching a value outside of the clock operation range between successive reset pulses.
17. The method of claim 16 wherein providing the error signal further comprises:
providing the error signal in response to a high frequency clock error limit being detected in response to the counter failing to reach a minimum value between successive reset pulses; or
providing the error signal in response to a low frequency clock error limit being detected in response to the counter reaching a maximum value between successive reset pulses.
18. The method of claim 14 further comprising: latching out a clock error signal in response to an enable signal.
19. The method according to claim 14 further comprising:
inputting the input clock signal to a first input of a first NAND logic gate and a first delay;
inputting an output of the first delay to a second inverted input of the first NAND logic gate; and
providing an enable pulse from an output of the first NAND logic gate to latch a clock error signal from a counter.
20. The method according to claim 19 further comprising:
inputting a delayed input clock signal to a first input of a second NAND logic gate and a second delay;
inputting an output of the second delay to a second inverted input of the second NAND logic gate; and
providing a reset pulse from an output of the second NAND logic gate for resetting the counter.
21. The method according to claim 14 further comprising:
generating at least one of an enable pulse, a reset pulse, or both a reset pulse and an enable pulse upon each corresponding rising and trailing edge of the input clock signal.
22. The method according to claim 21 further comprising comparing time periods between at least one of successive enable pulses or between success reset pulses to identify a misaligned clock duty cycle.