Self-aligned in-laid split gate memory and method of making
View Patent ↗A method includes forming a silicon nitride layer and patterning it to form a first opening and a second opening separated by a first portion of silicon nitride. Gate material is deposited in the first and second openings to form first and second select gate structures in the first and second openings. Second and third portions of silicon nitride layer are removed adjacent to the first and second gate structures, respectively. A charge storage layer is formed over the semiconductor device after removing the second and third portions. First and second sidewall spacers of gate material are formed on the charge storage layer and adjacent to the first and second gate structures. The charge storage layer is etched using the first and second sidewall spacers as masks. The first portion is removed. A drain region is formed in the semiconductor layer between the first and second gate structures.
1. A method of making a semiconductor device over a semiconductor layer, comprising:
forming a layer of silicon nitride over the semiconductor layer;
patterning the layer of silicon nitride to form a first opening and a second opening in the layer of silicon nitride separated by a first portion of the layer of silicon nitride;
depositing gate material in the first opening and the second opening to form a first select gate structure in the first opening and a second select gate structure in the second opening;
removing a second portion and a third portion of the layer of silicon nitride while leaving the first portion between the first and second select gate structure, wherein the second portion is adjacent to the first select gate structure and the third portion is adjacent to the second select gate structure;
forming a charge storage layer over the semiconductor device after removing the second and third portions;
forming a first sidewall spacer of gate material on the charge storage layer and adjacent to the first select gate structure and a second sidewall spacer of gate material on the charge storage layer and adjacent to the second select gate structure;
etching the charge storage layer using the first sidewall spacer and the second sidewall spacer as a mask; and
removing the first portion; and
forming a drain region in the semiconductor layer between the first and second select gate structures.
2. The method of claim 1 , wherein the step of depositing gate material comprises:
depositing a first layer of gate material that fills the first and second openings and extends over the silicon nitride layer; and
chemical mechanical polishing the first layer of gate material.
3. The method of claim 2 , wherein the step of forming a first sidewall spacer of gate material comprises:
depositing a second layer of gate material over the semiconductor layer, wherein the second layer of gate material is conformal; and
anisotropically etching the second layer of gate material so that portions of the second layer of gate material that are horizontal are removed and the portions of the second layer of gate material that are non-horizontal are retained.
4. The method of claim 3 , wherein the step of depositing the second layer of gate material is further characterized by the gate material of the second layer of gate material comprising polysilicon.
5. The method of claim 2 , wherein the step of depositing the first layer of gate material is further characterized by the gate material of the first layer of gate material comprising polysilicon.
6. The method of claim 1 , wherein the step of forming the drain region is further characterized as simultaneously forming a first source region in the semiconductor layer adjacent to the first sidewall spacer and a second source region in the semiconductor layer adjacent to the second sidewall spacer.
7. The method of claim 1 , further comprising performing a first threshold voltage adjust implant into the semiconductor layer after the step of patterning the layer of silicon nitride and before the step of depositing gate material in the first opening.
8. The method of claim 7 , further comprising performing a second threshold voltage adjust implant into the semiconductor layer after the step of removing the second and third portions of the layer of silicon nitride and before the step of forming the first sidewall spacer.
9. The method of claim 1 , wherein the step of forming a first sidewall spacer is further characterized by the first and second sidewall spacers being characterized as control gate structures.
10. The method of claim 1 , wherein the step of forming the charge storage layer is further characterized by the charge storage layer comprising nanocrystals.