IP Library Granted Patent US 8,508,282
Granted Patent B2
US 8,508,282 · App. 12/278,484 · Granted Aug 13, 2013

LIN bus network, integrated circuit and method of communicating thereon

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Quick Facts
Patent No.
US 8,508,282
App. No.
12/278,484
Granted
Aug 13, 2013
Kind
B2
Abstract

A LIN network comprises a transmit driver and a receive comparator for communicating low frequency signals on a single communication bus. The transmit driver is operably coupled to a high frequency detector to detect a high frequency component on the low frequency signal. In response to detecting the high frequency component the LIN network is arranged to perform one or both of the following: route the low frequency signal having a high frequency component through a low pass filter; and/or bypass the low frequency signal having a high frequency component from passing through an active device operably coupled between the transmit driver and the single communication bus.

Claims (39)

1. A linear interconnect networking (LIN) network comprising:

a transmit driver and a receive comparator for communicating on a single communication bus, wherein the transmit driver is operably coupled to a high frequency detector to detect a high frequency component on a low frequency LIN signal and in response to the detection of the high frequency the LIN network is arranged to perform one or both of the following:

route an average of the low frequency LIN signal having the high frequency component through a low pass filter; and

bypass the low frequency LIN signal having the high frequency component signal from being passed through an active device operably coupled between the transmit driver and the single communication bus; and

a first switch arranged in parallel to the active device and operably coupled to the high frequency detector such that the first switch is switched to a closed position in a high frequency loop to bypass the active device when the high frequency component is detected.

2. The LIN network of claim 1 wherein the active device is a diode.

3. The LIN network of claim 1 , wherein an output of the high frequency detector configures the LIN network to bypass the active device thereby removing a rectification effect on the low frequency LIN signal caused by the active device due to the high frequency component.

4. The LIN network of claim 1 further characterised in that the transmit driver is configured to operate in one of at least two modes utilising one of at least two loops.

5. The LIN network of claim 4 wherein one of the at least two loops is a high frequency mode loop that is selected in response to the detection of the high frequency component on the low frequency LIN signal.

6. The LIN network of claim 4 wherein the the one of the at least two loops incorporates the low pass filter when the high frequency component is detected.

7. The LIN network of claim 1 wherein a function of both the first switch and the active device is provided by a single PMOSFET.

8. The LIN network of claim 1 , a receiver node that receives a fed back average of the low frequency LIN signal and compares the fed back average of the low frequency LIN signal with a threshold voltage” to —The LIN network of claim 1 , comprising a receiver node that receives a fed back average of the low frequency LIN signal and compares the fed back average of the low frequency LIN signal with a threshold voltage.

9. An integrated circuit for use in a linear interconnect networking (LIN) network comprising:

a transmit driver and a receive comparator for communicating on a single communication bus, the transmit driver operably coupled to a high frequency detector to detect a high frequency component on a low frequency LIN signal, and in response to the detection of the high frequency component the integrated circuit is arranged to perform one or both of the following:

route an average of the low frequency LIN signal having the high frequency componet through a low pass filter; and

bypass the low frequency LIN signal having the high frequency component signal from being passed through an active device operably coupled between the transmit driver and the single communication bus; and

a first switch arranged in parallel to the active device and operably coupled to the high frequency detector such that the first switch is switched to a closed position in a high frequency loop to bypass the active device when the high frequency component is detected.

10. The integrated circuit of claim 9 wherein the active device is a diode.

11. The integrated circuit of claim 9 wherein an output of the high frequency detector configures the integrated circuit to bypass the active device thereby removing a rectification effect on the LIN low frequency signal caused by the active device due to the high frequency component.

12. The integrated circuit of claim 9 , wherein the transmit driver is configured to operate in one of at least two modes utilising one of at least two loops.

13. The integrated circuit of claim 12 wherein the one of the at least two loops is a high frequency mode loop that is selected in response to the detection of the high frequency component on the low frequency LIN signal.

14. The integrated circuit of claim 12 wherein the one of the at least two loops incorporates the low pass filter when the high frequency component is detected.

15. An integrated circuit for use in a linear interconnect networking (LIN) network comprising:

a transmit driver and a receive comparator for communicating on a single communication bus, the transmit driver operably coupled to a high frequency detector to detect a high frequency component on a low frequency LIN signal, and in response to the detection of the high frequency component the integrated circuit is arranged to perform one or both of the following;

route an average of the low frequency LIN signal having the high frequency component through a low pass filter; and

bypass the low frequency LIN signal having the high frequency component signal from being passed through an active device operably coupled between the transmit driver and the single communication bus; and

a receiver node that receives a fed back average of the low frequency LIN signal and compares the fed back average of the low frequency LIN signal with a threshold voltage.

16. A method of communication on a linear interconnect networking (LIN) network cormprising a transmit driver operably coupled to a single communication bus via an active device, the method comprising:

communicating a low frequency LIN signal having a high frequency component on a single communication bus:

detecting the high frequency component on the low frequency LIN signal;

in response to detecting, performing one or both of the following:

routing an average of the low frequency LIN signal having the high frequency component through a low pass filter; and

bypassing the low frequency LIN signal having the high frequency component signal from passing through the active device;

switching a first switch to a closed position in a high frequency loop when the high frequency component is detected, wherein the first switch is arranged in parallel to the active device and operably coupled to the high frequency detector; and

bypassing the active device in response to the first switch being switched to the closed position.

17. The method of claim 16 further comprising:

configuring the LIN network to bypass the active device to remove a rectification effect caused by the active device.

18. The method of claim 16 further comprising:

routing the low frequency LIN signal having the high frequency component through a high frequency mode loop selected in response to detecting the high frequency component.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0757 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 024085/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2010
From: SICARD, THIERRY
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 023850/0129 →
SECURITY AGREEMENT Recorded Dec 9, 2008
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 021936/0772 →