Controlling the access of master elements to slave elements over a communication bus
View Patent ↗A system comprises one or more slave elements operably coupled to a plurality of master devices. A central protection function is operably coupled to a first communication bus and configured to control data flow between the one or more slave elements and the plurality of master devices via the communication bus.
1. A system comprising:
one or more slave circuits operably coupled to a plurality of master devices, and
a central protection controller operably coupled to a first communication bus and configured to control data flow between the one or more slave circuits and the plurality of master devices via the first communication bus and arranged to protect access to the one or more slave circuits, the central protection controller comprising an internal validation checker to check whether protection settings assigned to the central protection controller are in conflict with existing system read-write memory settings, wherein the internal validation checker is to check whether the protection settings configure a RAM memory area of one of the one or more slave circuits as read only for all of the master devices, and thereby the RAM memory area cannot be written to by any of the master devices.
2. The system of claim 1 wherein the one or more slave circuits is/are slave memory elements; and the central protection controller is configured to protect access to the one or more slave memory elements, to receive a request to access the one or more slave memory elements, and to determine whether a requested memory area of the one or more slave memory elements can be validly accessed according to the protection settings assigned to the central protection controller.
3. The system of claim 1 , wherein the central protection controller is programmed with one-time protection settings.
4. The system of claim 1 , wherein the one or more slave circuits are operably coupled to an external bus and the central protection controller is configured to control access to or from the one or more slave circuits via the external bus.
5. The system of claim 1 , wherein the plurality of master devices comprise one or more of the following: a central processing unit, enhanced direct memory access, external bus interface, co-processor.
6. The system of claim 1 , wherein the system is located within a system-on-chip.
7. A method for controlling access of a plurality of master elements to one or more slave memory elements, comprising:
receiving, by a central protection engine operably coupled to a communication bus and configured to control data flow between one or more slave elements and the plurality of master devices via the communication bus, an assignment of protection settings controlling access by the master devices to the slave devices; and
checking, by the central protection engine whether a memory area of one of the one or more slave memory elements is inaccessible, wherein the checking comprises checking whether a RAM memory area of one of the one or more slave memory elements is configured as read only for all of the master elements, and thereby cannot be written to by any of the master elements.
8. The method of claim 7 , wherein:
the central protection engine is coupled to a memory management unit (MMU) of at least one of the plurality of master devices; and
the method further comprises dynamically addressing up-to-date memory space by the central protection engine.
9. The method of claim 7 , wherein the checking comprises checking whether the assigned protection settings are set in a contradictory configuration.
10. The system of claim 1 , wherein the first communication bus comprises a crossbar switch.
11. The system of claim 1 , wherein:
the central protection controller interfaces between the first communication bus and the plurality of master devices; and
the central protection controller is arranged to receive a request by one of the plurality of master devices to access one of the one or more slave circuits over the first communication bus and to grant the request, wherein no data transfer is initiated on the first communication bus without passing through the central protection controller.
12. The system of claim 1 , further comprising an interrupt controller to generate an interrupt if a requested memory area in a slave circuit cannot be validly accessed.
13. The system of claim 1 , wherein the one or more slave circuits are slave memory elements, the system comprises a trusted Operating System (OS) Kernel and associated device drivers, and a mode of the central protection controller is to grant full access rights to the (OS) Kernel and associated device drivers and is to limit access to individual tasks initiated by the OS.
14. The method of claim 7 , wherein:
the method further comprises:
receiving a request to access a memory area of one of the one or more slave memory elements;
determining not to grant the request; and
raising an error flag.
15. The system of claim 1 , wherein the internal validation checker comprises hardware.
16. A system comprising:
one or more slave circuits operably coupled to a plurality of master devices, a central protection controller (CPC) operably coupled to a first communication bus and configured to control data flow between the one or more slave circuits and the plurality of master devices via the first communication bus and configured to protect access to memory of the one or more slave circuits during a supervisory mode of the system; and
a Trusted Operating System (TOS) kernel, wherein the CPC is to allow the TOS kernel and associated device drivers to run with full access rights to the memory of the one or more slave circuits during the supervisory mode of the system and the CPC is to restrict access to the memory of the one or more slave circuits by invalidated software during the supervisory mode of the system.
17. The system of claim 16 , wherein the system is located within a system-on-chip.
18. The method of claim 7 , wherein the checking by the central protection controller comprises checking by hardware.
19. The system of claim 16 , wherein the plurality of master devices comprises one or more of the following:
a central processing unit;
an enhanced direct memory access;
an external bus interface; or
a co-processor.
20. The system of claim 16 , wherein the central protection controller is programmed with one-time protection settings.