Circuit and method for optimizing memory sense amplifier timing
View Patent ↗A memory has an array of memory cells, a word line driver, a sense amplifier, and a sense enable circuit. Each memory cell has a coupling transistor for coupling a storage portion to a bit line. The coupling transistors have an average threshold voltage and a maximum threshold voltage. The word line driver is coupled to the array and is for enabling a selected row of memory cells in the array. The sense amplifier detects a state of a memory cell in the selected row in response to a sense enable signal. The sense enable circuit provides the sense enable signal at a time based on the maximum threshold voltage. This timing enables the sense amplifier sufficiently late for low temperature operation while providing for faster operation at high temperature than would normally be achieved using just the average threshold voltage in providing timing of the sense enable signal.
1. A memory comprising:
an array of memory cells, wherein each memory cell comprises a coupling transistor for coupling a storage portion to a bit line, wherein a statistical average of threshold voltages of coupling transistors within the array is an average threshold voltage and at least one coupling transistor has a maximum possible threshold voltage;
a word line driver coupled to the array for enabling a selected row of memory cells in the array;
a sense amplifier for detecting a state of a memory cell in the selected row in response to a sense enable signal; and
a sense enable circuit for providing the sense enable signal at a time based on the maximum possible threshold voltage.
2. The memory of claim 1 , wherein the sense enable circuit comprises a voltage divider of a power supply voltage that provides an output based on a difference between the average threshold voltage and the maximum possible threshold voltage.
3. The memory of claim 2 , wherein the sense enable circuit comprises:
a first delay circuit that provides a partial match of delay through the word line driver;
a second delay circuit comprising a bit line portion based on the bit line and on precharge circuitry and a delay configuration that models the average threshold voltage; and
a third delay circuit providing an input to the delay configuration causing the delay configuration to respond as modeling the maximum possible threshold voltage.
4. The memory of claim 3 , wherein the voltage divider has a first terminal and a second terminal and comprises:
a first resistor having a first terminal as the first terminal of the voltage divider and a second terminal; and
a second resistor having a first terminal coupled to the second terminal of the first resistor and a second terminal as the second terminal of the voltage divider, wherein the second terminal of the first resistor and the first terminal of the second resistor form an output of the voltage divider.
5. The memory of claim 4 , wherein the third delay circuit comprises:
a first transistor having a first current electrode coupled to a first power supply terminal, a control electrode coupled to the first delay circuit, and a second current electrode coupled to a first terminal of the voltage divider;
wherein:
the output of the voltage divider is coupled to the delay configuration of the second delay circuit.
6. The memory of claim 5 , wherein the second delay circuit comprises:
a second transistor having a control electrode coupled to the output of the voltage divider, a first current electrode coupled to the bit line portion, and a second current electrode; and
a load having a first terminal coupled to the second current electrode of the second transistor and a second terminal coupled to a second power supply terminal.
7. The memory of claim 6 , wherein the load models a portion of the storage portion.
8. The memory of claim 6 , wherein the third delay circuit further comprises a third transistor having a first current electrode coupled to the output of the voltage divider, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to the second power supply terminal, wherein the third transistor is N type and the first transistor is P type.
9. The memory of claim 5 , wherein the second delay circuit comprises:
a second transistor having a control electrode coupled to the second current electrode of the first transistor, a first current electrode coupled to the bit line portion, and a second current electrode; and
a load having a first terminal coupled to the second current electrode of the second transistor and a second terminal coupled to the output of the voltage divider.
10. The memory of claim 9 , wherein the third delay circuit further comprises a third transistor having a first current electrode coupled to the output of the voltage divider, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to a second power supply terminal, wherein the third transistor is N-conductivity type and the first transistor is P-conductivity type.
11. The memory of claim 1 , wherein the sense enable circuit and the word line driver are responsive to a word line enable signal.
12. A memory comprising:
an array of memory cells:
a word line driver coupled to the array for enabling a selected row of memory cells in the array;
a sense amplifier for detecting a state of a memory cell in the selected row in response to a sense enable signal; and
a sense enable circuit for providing the sense enable signal at a time based on a maximum possible threshold voltage of predetermined transistors in the array of memory cells, wherein the sense enable circuit comprises:
a first resistor having a first terminal as a first terminal of a voltage divider and a second terminal;
a second resistor having a first terminal coupled to the second terminal of the first resistor and a second terminal as a second terminal of the voltage divider comprising the first resistor and the second resistor, wherein the second terminal of the first resistor and the first terminal of the second resistor form an output of the voltage divider;
a first delay circuit having an input responsive to a word line enable signal and an output;
a first transistor having a first current electrode coupled to a first power supply terminal, a control electrode coupled to the output of the first delay circuit, and a second current electrode coupled to the first terminal of the voltage divider; and
a second delay circuit characterized as modeling a bit line and a memory cell having an input coupled to the output of the voltage divider and an output that provides the sense enable signal.
13. The memory of claim 12 , wherein the memory cells of the array are characterized by having coupling transistors that couple a storage portion to a bit line, wherein the coupling transistors collectively have an average threshold voltage and at least one has a maximum possible threshold voltage, wherein the voltage divider is further characterized as providing a voltage at the output of the voltage divider representative of a difference between the average threshold voltage and the maximum possible threshold voltage.
14. The memory of claim 13 , wherein a difference between a reference voltage and a supply voltage at the first power supply terminal is equal to the difference between the average threshold voltage and the maximum possible threshold voltage.
15. The memory of claim 13 , wherein the second delay circuit comprises:
a dummy bit line;
a load; and
a second transistor having a first current electrode coupled to the dummy bit line, a control electrode coupled to the output of the voltage divider, and a second current electrode coupled to the load.
16. The memory of claim 13 , wherein the second delay circuit comprises:
a dummy bit line;
a load; and
an active device having a first current electrode coupled to the dummy bit line, a control electrode coupled to the output of the voltage divider, and a second current electrode coupled to the load, wherein the active device closely approximates the average threshold voltage.
17. The memory of claim 16 wherein the active device comprises a plurality of transistors matching electrical parameters of the coupling transistors, and the load comprises a plurality of individual devices each modeling a storage portion of the memory cells.
18. The memory of claim 13 , wherein the second delay circuit comprises:
a dummy bit line;
a load having a first terminal coupled to the output of the voltage divider and a second terminal; and
an active device having a first current electrode coupled to the dummy bit line, a control electrode coupled to the second current electrode of the first transistor, and a second current electrode coupled to a second terminal of the load.
19. The memory of claim 13 , wherein the second delay circuit comprises an active device and a load that have a gate-to-source voltage adjusted by the voltage divider to provide a model of a coupling transistor having a maximum possible threshold voltage.
20. A method of enabling a sense amplifier of a memory having an array of memory cells, comprising:
obtaining an average threshold voltage of coupling transistors that couple a storage portion of the memory cells to a bit line;
obtaining a maximum possible threshold voltage of the coupling transistors;
enabling the sense amplifier in response to a sense enable signal;
providing a device as modeling the average threshold voltage;
generating a reference voltage, wherein the reference voltage is representative of a difference between the maximum possible threshold voltage and the average threshold voltage; and
delaying a word line enable signal to produce an output enable signal by applying the reference voltage to the device, the output enable signal enabling the sense amplifier.