Cache snoop limiting within a multiple master data processing system
View Patent ↗In a data processing system, access to a cache in response to access requests from first processing circuitry and snoop requests resulting from a transaction performed by second processing circuitry are arbitrated. Accesses to the cache are monitored to determine if the first processing circuitry is prevented from accessing the cache for more than a threshold amount of time. A signal is generated to indicate when the first processing circuitry has been prevented from accessing the cache for more than the threshold amount of time.
1. A method comprising:
arbitrating access to a cache between access requests from first processing circuitry and snoop requests resulting from a transaction performed by second processing circuitry;
monitoring accesses to the cache to determine if the first processing circuitry is prevented from accessing the cache for more than a threshold amount of time; and
generating a signal to indicate when the first processing circuitry has been prevented from accessing the cache for more than the threshold amount of time.
2. The method of claim 1 further comprising:
generating the signal in response to determining that the first processing circuitry has been prevented from accessing the cache for a predetermined number of data processing cycles.
3. The method of claim 2 further comprising:
generating the signal also in response to determining that the first processing circuitry has been prevented from accessing the cache for at least the predetermined number of data processing cycles over a predetermined time period.
4. The method of claim 3 further comprising:
dynamically altering the predetermined number of data processing cycles in response to system activity within a data processing system comprising the cache, first processing circuitry and second processing circuitry.
5. The method of claim 1 further comprising:
generating the signal also in response to determining that the first processing circuitry has been prevented from accessing the cache for at least a predetermined number of data processing cycles over a predetermined time period.
6. The method of claim 5 further comprising:
dynamically altering the predetermined number of data processing cycles for use in a second time period subsequent to the predetermined time period in response to a previous value of a number of data processing cycles that the first processing circuitry is prevented from accessing the cache during the predetermined time period.
7. The method of claim 1 further comprising:
in response to generating the signal, preventing snoop requests to the cache for a predetermined amount of time.
8. The method of claim 1 further comprising:
in response to generating the signal, limiting snoop requests to a predetermined amount of time during a timeframe of predetermined duration subsequent to generating the signal.
9. The method of claim 1 further comprising:
generating a second signal for indicating when the second processing circuitry has been prevented from accessing the cache for more than the threshold amount of time.
10. A system comprising:
a first master and a second master coupled via a system interconnect, the first master comprising:
a cache memory;
first processing circuitry coupled to the cache memory; and
an arbiter coupled to the first processing circuitry and the cache memory, the arbiter arbitrating access to the cache memory between access requests from the first master and snoop requests resulting from a transaction performed by the second master, the arbiter generating a signal to indicate when the first master has been prevented from accessing the cache memory;
the system further comprising:
coherency logic coupled to the first master and the second master, the coherency logic using the signal to indicate when the first master has been prevented from accessing the cache memory for more than a predetermined amount of time.
11. The system of claim 10 wherein the coherency logic uses the signal to determine that the first master has been prevented from accessing the cache memory for a predetermined number of data processing cycles.
12. The system of claim 11 wherein the coherency logic uses the signal also to determine that the first master has been prevented from accessing the cache memory for at least a predetermined number of data processing cycles over a predetermined time period.
13. The system of claim 11 wherein the coherency logic dynamically alters the predetermined number of data processing cycles in response to system activity within the system.
14. The system of claim 11 wherein the coherency logic uses the signal to determine that the first master has been prevented from accessing the cache memory for at least a predetermined number of data processing cycles over a predetermined time period.
15. The system of claim 11 wherein the coherency logic dynamically alters the predetermined number of data processing cycles for use in a second time period subsequent to the predetermined time period in response to a previous value of the predetermined number of data processing cycles.
16. The system of claim 11 wherein the coherency logic prevents snoop requests from the second master to the cache memory for a predetermined amount of time in response to receiving the signal.
17. The system of claim 11 wherein the second master generates a second signal for indicating when the second master has been prevented from accessing the cache memory, the cache memory limiting cache accesses from the first master when the second master has been prevented from accessing the cache memory for more than a second predetermined amount of time.