Electronic device including a semiconductor fin
View Patent ↗An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.
1. An electronic device comprising:
an insulating layer;
a semiconductor fin overlying the insulating layer;
a semiconductor layer overlying the semiconductor fin, wherein the semiconductor layer has a first portion and a second portion that are spaced-apart from each other;
a conductive member lying between and spaced-apart from the first portion of the semiconductor layer and the second portion of the semiconductor layer, and overlying and spaced-apart from the semiconductor fin; and
a metal-semiconductor layer overlying the semiconductor layer,
wherein:
a first interface lies between the semiconductor layer and the metal-semiconductor layer;
the conductive member includes a semiconductor portion, a metal-semiconductor portion, and a second interface therebetween; and
the first interface has a first surface roughness value, and the second interface has a second surface roughness value that is greater than the first surface roughness value.
2. The electronic device of claim 1 , wherein the metal-semiconductor layer has a substantially uniform thickness.
3. The electronic device of claim 1 , wherein:
the semiconductor fin and the semiconductor layer each comprise silicon, carbon, germanium, a compound alloy or any combination thereof; and
the metal-semiconductor layer comprises nickel, tungsten, titanium, cobalt, erbium, platinum, or any combination thereof.
4. The electronic device of claim 3 , wherein:
the semiconductor fin and the semiconductor layer comprise a same semiconductor material;
the semiconductor fin has a first semiconductor composition; and
the semiconductor layer has a second semiconductor composition different from the first semiconductor composition.
5. The electronic device of claim 4 , wherein:
the first semiconductor composition includes a first ratio of silicon:germanium; and
the second semiconductor composition includes a second ratio of silicon:germanium, wherein the second ratio is different from the first ratio.
6. The electronic device of claim 1 , wherein an averaged concentration of a dopant in the semiconductor layer is higher than an averaged concentration of the dopant in the semiconductor fin.
7. The electronic device of claim 1 , wherein the semiconductor fin and the semiconductor layer have different lattice constants.
8. The electronic device of claim 1 , wherein the electronic device comprises a transistor including:
the conductive member, wherein the conductive member includes gate electrode portions that lie adjacent to opposing sides of the semiconductor fin;
a first source/drain region;
a second source/drain region spaced-apart from the first source/drain region; and
a channel region lying within the semiconductor fin and between the first source/drain region and the second source/drain region, wherein the channel region is configured, such that when the transistor would be on, charge carriers would flow through the channel region in a direction substantially parallel to a primary surface of the insulating layer.
9. The electronic device of claim 8 , wherein the transistor further comprises a gate dielectric layer having a dielectric constant greater than 8.
10. The electronic device of claim 8 , wherein the channel region does not include the semiconductor layer.
11. The electronic device of claim 1 , wherein the semiconductor layer comprises a silicon germanium layer.
12. The electronic device of claim 1 , wherein the first surface roughness value is not more than approximately 2 nm.
13. The electronic device of claim 1 , wherein the second surface roughness value is greater than approximately 2 nm.
14. An electronic device comprising:
an insulating layer;
a semiconductor fin overlying the insulating layer;
a semiconductor layer abutting the semiconductor fin, wherein the semiconductor layer includes a dopant and has a first portion and a second portion that are spaced-apart from each other; and
a conductive member lying between and spaced-apart from the first portion of the semiconductor layer and the second portion of the semiconductor layer, and overlying and spaced-apart from the semiconductor fin,
wherein the electronic device includes a transistor that comprises a first source/drain region, a second source/drain region, and a channel region, wherein:
the first source/drain region includes a first portion of the semiconductor layer;
the second source/drain region is spaced apart from the first source/drain region and includes a second portion of the semiconductor layer; and
the channel region does not include the semiconductor layer.
15. The electronic device of claim 14 , further including a metal-semiconductor layer overlying the semiconductor layer.
16. The electronic device of claim 14 , wherein the transistor further comprises a gate electrode, wherein:
the gate electrode includes gate electrode portions of the conductive member that lie adjacent to opposing sides of the semiconductor fin; and
the channel region lies within the semiconductor fin and between the first source/drain region and the second source/drain region, wherein the channel region is configured, such that when the transistor would be on, charge carriers would flow through the channel region in a direction substantially parallel to a primary surface of the insulating layer.
17. The electronic device of claim 14 , wherein:
the semiconductor fin includes a wall surface and has a first germanium content;
the semiconductor layer has a second germanium content higher than the first germanium content.
18. The electronic device of claim 14 , further comprising a metal-semiconductor layer overlying the semiconductor fin, wherein:
a first interface lies between the semiconductor layer and the metal-semiconductor layer; and
the conductive member includes a semiconductor portion, a metal-semiconductor portion, and a second interface therebetween.
19. The electronic device of claim 14 , wherein the transistor further comprises a gate dielectric layer having a dielectric constant greater than 8.
20. The electronic device of claim 14 , wherein the semiconductor layer comprises a silicon germanium layer.