IP Library Granted Patent US 8,350,921
Granted Patent B2
US 8,350,921 · App. 12/598,294 · Granted Jan 8, 2013

Video processing system, integrated circuit, system for displaying video, system for generating video, method for configuring a video processing system, and computer program product

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Quick Facts
Patent No.
US 8,350,921
App. No.
12/598,294
Granted
Jan 8, 2013
Kind
B2
Abstract

A video processing system may include a video input and a video output for outputting manipulated video images. The system may have a video processing chain connecting the video input to the video output. The chain may include a series connection of two or more video processing components. The components may each include a component input for receiving video images and a component output for outputting processed video images. A control input may be present for controlling the video processing component to be in an enabled or a disabled state. The video processing component may be arranged to obtain in the enabled state the processed video images by performing a respective processing operation on the received video images; and to obtain in the disabled state the processed video images by forwarding the received video images to the component output without performing the processing operation.

Claims (65)

1. A video processing system comprising:

a video input;

a video output for outputting at least one manipulated video image;

a video processing chain connecting said video input to said video output, said chain including a series connection of at least two video processing components, each including:

a component input for receiving at least one video image;

a component output for outputting at least one processed video image;

a control input for controlling the video processing component to be in an enabled state or a disabled state, said video processing component being arranged to obtain in said enabled state the processed video image by performing a respective processing operation on the received video images, in which disabled state the processed video image is inputted to a node downstream of the video processing component in the disabled state without being subjected to said processing operation.

2. A video processing system as claimed in claim 1 , including at least two video outputs and at least two video processing chains, each of said chains connecting said video input to a respective one of said video outputs.

3. A video processing system as claimed in claim 2 , wherein:

said video input is connectable to a camera;

said at least two video outputs comprising:

a first video output connectable to a display device for visually outputting the video images and

a second video output connectable to a video coding device or a video storage device, said at least two video processing chains include:

a first chain, connecting said video input to said first video output, arranged to pre-process said at least one video image received at the video input in a manner suitable to be outputted by said display device, and

a second chain, connecting said video input to said second video output, arranged to pre-process the video images received at the video input in a manner suitable for said video coding device or a video storage device.

4. A video processing system as claimed in claim 2 , wherein at least one of said at least two chains is a branch of another of said at least two chains.

5. A video processing system as claimed in claim 1 , comprising:

a video input connectable to a video coding device or a video storage device;

a video display output connectable to a display device; and

a post-processing chain connecting said video input to said second video output, said post-processing chain is arranged to post-process the video images received at the video input in a manner suitable to be outputted by said device.

6. A video processing system as claimed in claim 1 , wherein at least one of the video processing components includes a configuration control input for configuring at least one parameter of the processing operation.

7. An integrated circuit including a video processing system as claimed in claim 1 .

8. A video processing system as claimed in claim 3 , wherein at least one of said at least two chains is a branch of another of said at least two chains.

9. A video processing system as claimed in claim 3 , including:

a video input connectable to a video coding device or a video storage device;

a video display output connectable to a display device; and

a post-processing chain connecting said video input to said second video output, said post-processing chain is arranged to post-process the video images received at the video input in a manner suitable to be outputted by said display device.

10. A video processing system as claimed in claim 4 , including:

a video input connectable to a video coding device or a video storage device;

a video display output connectable to a display device; and

a post-processing chain connecting said video input to said second video output, said post-processing chain is arranged to post-process the video images received at the video input in a manner suitable to be outputted by said display device.

11. A video processing system as claimed in claim 2 , including:

a video input connectable to a video coding device or a video storage device;

a video display output connectable to a display device; and

a post-processing chain connecting said video input to said second video output, said post-processing chain is arranged to post-process the video images received at the video input in a manner suitable to be outputted by said display device.

12. A video processing system as claimed in claim 2 , wherein at least one of the video processing components includes a configuration control input for configuring at least one parameter of the processing operation.

13. A system for displaying video, including

a video processing system as claimed in claim 1 and

a display device connected to a video output of said video processing system.

14. A system for acquiring video, comprising:

a camera;

a video processing system as claimed in claim 1 connected with a video input to said camera, for receiving unprocessed video images from said camera; and optionally

a video coding device and/or a video storage device connected to a video output of said video processing system.

15. A method for configuring a video processing system, the method comprising:

enabling or disabling at least one video processing component of a video processing system, wherein the video processing system comprises:

a video input;

a video output for outputting at least one manipulated video image;

a video processing chain connecting said video input to said video output, said chain including a series connection of at least two video processing components, each including:

a component input for receiving at least one video image;

a component output for outputting at least one processed video image;

a control input for controlling the video processing component to be in an enabled state or a disabled state, said video processing component being arranged to obtain in said enabled state the processed video image by performing a respective processing operation on the received video images, in which disabled state the processed video image is inputted to a node downstream of the video processing component in the disabled state without being subjected to said processing operation.

16. A method as claimed in claim 15 , including at least two video outputs and at least two video processing chains, each of said chains connecting said video input to a respective one of said video outputs.

17. A method as claimed in claim 16 , wherein:

said video input is connectable to a camera;

said at least two video outputs comprising:

a first video output connectable to a display device for visually outputting the video images and

a second video output connectable to a video coding device or a video storage device, said at least two video processing chains include:

a first chain, connecting said video input to said first video output, arranged to pre-process said at least one video image received at the video input in a manner suitable to be outputted by said display device, and

a second chain, connecting said video input to said second video output, arranged to pre-process the video images received at the video input in a manner suitable for said video coding device or a video storage device.

18. A method as claimed in claim 16 , wherein at least one of said at least two chains is a branch of another of said at least two chains.

19. A method as claimed in claim 15 , comprising:

a video input connectable to a video coding device or a video storage device;

a video display output connectable to a display device; and

a post-processing chain connecting said video input to said second video output, said post-processing chain is arranged to post-process the video images received at the video input in a manner suitable to be outputted by said display device.

20. A method as claimed in claim 15 , wherein at least one of the video processing components includes a configuration control input for configuring at least one parameter of the processing operation.

Assignments (26)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037355/0723 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →