Programmable bias for a memory array
View Patent ↗A method determines a body bias for a memory cell. A supply voltage is applied to the memory cell and a bit line is precharged to a voltage lower than the supply voltage. A programmable bias voltage circuit provides a bias voltage to the memory cell in response to values on its input. Initial test values for the input are used. The memory cell is tested to determine a pass or a fail condition of the memory cell. The initial values are retained as the input values if the memory cell passes. If the memory cell fails, the memory cell is tested at changed values for the input. If the changed input values result in the memory cell being in a pass condition, the programmable bias voltage circuit is configured, in non-volatile fashion, to have the changed input values.
1. A method for determining a body bias for a memory cell coupled to a bit line, comprising:
applying a first supply voltage to the memory cell and precharging the bit line to a voltage lower than the first supply voltage as a first test condition representative of a first mode of operation of the memory cell;
providing a programmable bias voltage circuit that provides a bias voltage to the memory cell based on input values;
applying initial test values as the input values;
testing the memory cell with the memory cell in the first test condition using the initial test values to determine a pass or a fail condition of the memory cell and retaining the initial values as the input values if the memory cell has a pass condition; and
if the memory cell has a fail condition, testing the memory cell with the memory cell in the first test condition at changed input values that are changed from the initial values, and if the changed input values result in the memory cell being in a pass condition, configuring, in non-volatile fashion, the programmable bias voltage circuit to have the changed input values.
2. The method of claim 1 , wherein the configuring is further characterized by programming electrical fuses.
3. The method of claim 1 , further comprising:
applying the first supply voltage to the memory cell and precharging the bit line to the first supply voltage as a second test condition, wherein second test condition is representative of a second mode of operation of the memory cell;
applying second initial test values as the input values;
testing the memory cell with the memory cell in the second test condition using the second initial test values to determine a pass or a fail condition of the memory cell and retaining the second initial values as the input values for the second mode of operation if the memory cell has a pass condition; and
if the memory cell has a fail condition, testing the memory cell with the memory cell in the second test condition at second changed input values that are changed from the second initial values, and if the second changed input values result in the memory cell being in a pass condition, configuring, in non-volatile fashion, the programmable bias voltage circuit to have the second changed input values for use in the second mode of operation.
4. The method of claim 3 , wherein the second mode of operation is a higher speed mode of operation than the first mode.
5. The method of claim 1 , wherein the memory cell is a static random access memory cell having a plurality of N channel transistors in a P well, wherein the step of providing the programmable bias voltage circuit is further characterized by having an output directly connected to the P well.
6. The method of claim 1 wherein the memory cell is a static random access memory cell having a plurality of P channel transistors in an N well, wherein the step of providing the programmable bias voltage circuit is further characterized by having an output directly connected to the N well.
7. The method of claim 6 , wherein the static random access memory cell has a plurality of N channel transistors in a P well, further comprising:
providing a second programmable bias voltage circuit that provides a bias voltage to the P well;
applying second initial test values as the input values of the second programmable bias voltage circuit;
wherein the testing the memory cell with the memory cell in the first test condition is further characterized as using the second initial test values and retaining the second initial values as the input values of the second programmable bias voltage circuit if the memory cell has a pass condition; and
wherein if the memory cell has the fail condition, testing the memory cell with the memory cell in the first test condition at second changed input values that are changed from the second initial values, and if the second changed input values result in the memory cell being in a pass condition, configuring, in non-volatile fashion, the second programmable bias voltage circuit to have the second changed input values.
8. The method of claim 1 , wherein the step of applying a first supply voltage to the memory cell and precharging the bit line to a voltage lower than the first supply voltage as a first test condition representative of a first mode of operation of the memory cell further comprises applying the first supply voltage to a word line coupled to the memory cell.
9. The method of claim 1 , wherein the step of applying a first supply voltage to the memory cell and precharging the bit line to a voltage lower than the first supply voltage as a first test condition representative of a first mode of operation of the memory cell is further characterized by the voltage lower than the first supply voltage is more than fifteen percent below the first power supply voltage.
10. A method of providing a body bias to memory cells of a memory array having word lines and bit lines, comprising
providing a first programmable voltage circuit having an output for providing the body bias responsive to a first digital input signal;
applying a first voltage as a power supply voltage to the memory array;
precharging the bit lines to a second voltage more than fifteen percent lower than the first voltage;
providing the first digital input signal at first initial values;
testing the memory array;
if the memory array passes the testing, retaining the first initial values;
if the memory array fails the testing, changing the values of the first digital signal to values selected among a group of available values and re-testing the memory array until one of a group consisting of two events occurs, wherein a first event of the two events comprises the first digital signal has been changed to all of the values of the group of available values and a second event of the two events comprises the memory array passes the test using one of the available values; and
programming, in non-volatile fashion, the one of the available values for use as the first digital input signal of the first programmable voltage circuit.
11. The method of claim 10 , wherein the step of programming comprises programming electrical fuses.
12. The method of claim 10 , further comprising
providing a second programmable voltage circuit having an output for providing a second body bias responsive to a second digital input signal;
providing the second digital input signal at second initial values;
wherein if the memory array passes the testing, retaining the second initial values;
wherein if the memory array fails the testing, changing the values of the second digital signal to values selected among a second group of available values and re-testing the memory array until one of a group consisting of a third event and a fourth event, wherein the third event comprises the second digital signal has been changed to all of the values of the second group of available values and a fourth event comprises the memory array passes the test using one of the values of the second group of available values; and
programming, in non-volatile fashion, the second digital signal to the one of the values of the second group of available values.
13. The method of claim 10 , wherein:
the step of precharging the bit lines is further characterized as, for a second mode of operation, precharging the bit lines to the first voltage;
the providing the first digital input signal is further characterized as being provided at second initial values;
if the memory array passes the testing, retaining the second initial values;
if the memory array fails the testing, changing the values of the first digital signal to values selected among a second group of available values and re-testing the memory array until one of a group consisting of a third and a fourth event occurs, wherein a third event comprises the first digital signal has been changed to all of the values of the second group of available values and a fourth event of the two events comprises the memory array passes the test using one of the second group of available values; and
programming, in non-volatile fashion, the one of the second group of available values for use as the first digital input signal of the first programmable voltage circuit.
14. The method of claim 13 , further comprising switching between the one of the first group of available values and the one of the second group of available values for use as the first digital input signal of the first programmable voltage circuit.
15. A system comprising:
a memory array comprising memory cells, word lines, bit lines, a power supply input, and a first body bias input,
bit line precharge means for precharging the bit lines to a voltage below a power supply voltage applied at the power supply input;
a built in self test (BIST) engine coupled to the memory array and the storage unit;
a storage unit providing a first digital output; and
a programmable charge pump or a programmable regulator having a supply output coupled to the first body bias input and a programming input coupled to the first digital output.
16. The system of claim 15 , wherein the storage unit is non-volatile.
17. The system of claim 16 , wherein the storage unit is an electrical fuse bank, further comprising a fuse processor coupling the BIST engine to the electrical fuse bank.
18. The system of claim 15 , wherein:
the bit line precharge means is for precharging the bit lines to a voltage at least 15 percent below the power supply voltage in a first mode and for precharging the bit lines to the power supply voltage in a second mode; and
the storage unit is for providing a second digital output for use in the second mode;
further comprising:
a multiplexer coupled between the input of the programmable charge pump or the programmable regulator and the storage unit for selecting between the first and second digital signals.
19. The system of claim 15 , wherein the first body bias input is directly connected to bodies of N channel transistors of the memory cells.
20. The system of claim 19 , wherein the storage unit is for providing a second digital output, further comprising:
a second body bias input directly connected to bodies of P channel transistors of the memory cells; and
a second programmable charge pump or a second programmable regulator having a supply output coupled to the second body bias input and a programming input coupled to the second digital output.