Integrated circuit and a method for testing a multi-tap integrated circuit
View Patent ↗An integrated circuit that includes a controller for defining a test path that comprises at least one test access port out of multiple test access ports characterized by further comprising at least one multi-bit bypass logic for bypassing at least one of the multiple test access ports and for affecting a length of the test path. Conveniently, the length of the test path remains substantially fixed regardless of changes in a configuration of the test path. A method for testing an integrated circuit, the method includes a stage of propagating test signals across a test path. Whereas the method is characterized by a stage of defining a configuration of the test path, whereas the test path comprises at least one components out of at least one test access port and at least one bypass access logic; whereas the at least one multi-bit bypass logic bypass at least one of the multiple test access ports and affect a length of the test path.
1. An integrated circuit comprising:
a controller for defining a test path that comprises at least one test access port out of multiple test access ports comprising:
at least one multi-bit bypass logic for bypassing at least one of the multiple test access ports and for affecting a length of the test path, wherein the length of the test path remains substantially fixed regardless of changes in a configuration of the test path, wherein a bypass logic has equivalent data paths and equivalent instruction paths to those of a test access port it bypasses.
2. The integrated circuit according to claim 1 , whereas a length of at least one multi-bit bypass logic corresponds to a length of an internal test path within a corresponding bypassed test access port.
3. The integrated circuit according to claim 1 , further adapted to select between test paths of differing lengths.
4. The integrated circuit according to claim 3 wherein the integrated circuit comprises a pin for receiving a selection signal.
5. The integrated circuit according to claim 1 , wherein at least one bypass logic comprises at least one data register and at least one instruction register.
6. The integrated circuit according to claim 1 , wherein at least one bypass logic comprises a TAP controller.
7. The integrated circuit according to claim 1 , wherein the test access ports are IEEE 1149.1 compliant.
8. The integrated circuit according to claim 1 , wherein the controller comprises a test access port selection block.
9. The integrated circuit according to claim 1 , wherein the controller comprises a test access port.
10. The integrated circuit of claim according to claim 9 , wherein at least one test access port operates at a clock frequency that differs from a clock frequency of at least one other test access port.
11. A method for testing an integrated circuit, the method comprises:
propagating test signals across a test path; and
a stage of defining a configuration of the test path;
whereas the test path comprises at least one components out of at least one test access port and at least one bypass access logic;
whereas the at least one multi-bit bypass logic bypass at least one of the multiple test access ports and affect a length of the test path, wherein the length of the test path remains substantially fixed regardless of changes in a configuration of the test path;
whereas a length of at least one multi-bit bypass logic corresponds to a length of an internal test path within a corresponding bypassed test access port.
12. The method according to claim 9 , whereas the stage of defining further comprises selecting between test paths of differing lengths.
13. The method according to claim 11 , wherein at least one bypass logic comprises at least one data register and at least one instruction register.
14. The method according to claim 11 , wherein at least one bypass logic comprises a TAP controller.
15. The method according to claim 11 , wherein the test access ports are IEEE 1149.1 compliant.
16. The method of claim according to claim 11 , wherein at least one test access port operates at a clock frequency that differs from a clock frequency of at least one other test access port.
17. The method of claim according to claim 16 , wherein at least one bypass logic comprises a TAP controller.
18. A method for testing an integrated circuit, the method comprises:
propagating test signals across a test path; and
a stage of defining a configuration of the test path;
whereas the test path comprises at least one components out of at least one test access port and at least one bypass access logic;
whereas the at least one multi-bit bypass logic bypass at least one of the multiple test access ports and affect a length of the test path, wherein the length of the test path remains substantially fixed regardless of changes in a configuration of the test path;
wherein a bypass logic has equivalent data paths and equivalent instruction paths to those of a test access port it bypasses.