IP Library Granted Patent US 7,202,182
Granted Patent B2
US 7,202,182 · App. 10/882,482 · Granted Apr 10, 2007

Method of passivating oxide/compound semiconductor interface

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Quick Facts
Patent No.
US 7,202,182
App. No.
10/882,482
Granted
Apr 10, 2007
Kind
B2
Abstract

The present invention provides a method of passivating an oxide compound disposed on a III-V semiconductor substrate. The method is intended for use with dielectric stacks, gallate compounds, and gallium compounds used in gate quality oxide layers. The method includes heating a semiconductor structure at an elevated temperature of between about 230° C. and about 400° C. The semiconductor structure is exposed to an atmosphere that is supersaturated with water vapor or vapor of deuterium oxide. The exposure takes place at elevated temperature and continues for a period of time between about 5 minutes to about 120 minutes. It has been found that the method of the present invention results in a semiconductor product that has significantly improved performance characteristics over semiconductors that are not passivated, or that use a dry hydrogen method of passivation.

Claims (29)

1. A method for passivating oxide-semiconductor materials comprising the steps of:

providing a semiconductor structure comprising a III-V material on a gallium oxide based dielectric material over the III-V material, wherein the structure comprises an epitaxial layer disposed on a III-V substrate and the gallium oxide based dielectric material is a dielectric stack disposed on top of the epitaxial layer;

heating the semiconductor structure; and

exposing the semiconductor structure to a vapor of water or deuterium oxide or water and deuterium oxide.

2. The method according to claim 1 wherein the dielectric stack is disposed on top of the epitaxial layer.

3. The method according to claim 1 further comprising the steps of forming a layer of gate metal over the dielectric stack.

4. The method according to claim 1 further comprising the step of exposing the semiconductor structure for a time period of between about 5 minutes to about 120 minutes.

5. The method according to claim 4 wherein the time of exposure is between about 20 to about 40 minutes.

6. The method according to claim 1 wherein the heating step heats the semiconductor structure at a temperature of between about 230° C. to about 400° C.

7. The method according to claim 6 wherein the heating step heats the semiconductor structure at a temperature of between about 270° C. to about 320° C.

8. A method of passivating a deposited oxide compound III-V semiconductor interface comprising the steps of:

heating a source of liquid water or deuterium oxide so as to boil the liquid;

transferring vapor of water or deuterium oxide to a vessel;

heating a semiconductor material in a vessel at a temperature between approximately 230° C. and approximately 400° C., the semiconductor material comprising a III-V material and a gallium oxide based dielectric material over the III-V material; and

exposing the semiconductor material to the vapor for a time of between about 5 to about 120 minutes.

9. The method according to claim 8 wherein the step of heating a source of liquid water or deuterium oxide further comprises beating the water or deuterium oxide in a bubbler.

10. The method according to claim 8 wherein the step of heating a semiconductor material further comprises heating a semiconductor material in a furnace.

11. The method according to claim 8 wherein the step of heating a semiconductor material further comprises use of heating coils disposed in proximity to the vessel.

12. The method according to claim 8 wherein the vessel comprises a quartz tube.

13. The method according to claim 8 wherein the step of heating a semiconductor material comprises heating the semiconductor material at a temperature of between about 270° C. to about 320° C.

14. The method according to claim 8 wherein the step of exposing the semiconductor material further comprises exposing the semiconductor material for a time of between about 20 to about 40 minutes.

15. The method according to claim 8 wherein the step of transferring vapor further comprises transferring the vapor from the bubbler to the vessel through a tube.

16. The method according to claim 15 further comprising transferring the vapor through a tube with a carrier gas.

17. A method for passivating a gate oxide on a III-V compound semiconductor substrate comprising the steps of:

providing a multilayer semiconductor structure comprising a III-V substrate, an epitaxial layer deposited on one side of the III-V substrate, and a gallate/gallium oxide layer on one side of the epitaxial layer;

heating the semiconductor structure at a temperature of between about 230° C. to about 400° C.; and

exposing the semiconductor structure to a vapor of water or deuterium oxide or water and deuterium oxide for a time of between about 5 minutes to about 120 minutes.

18. The method according to claim 17 wherein the gallate/gallium oxide layer comprises a GdGaO/Ga 2 O 3 dielectric stack wherein the gallate compound may have gadolinium and gallium in differing stoichiometries.

19. The method according to claim 17 wherein the step of exposing the semiconductor structure to vapor further comprises exposing the semiconductor structure to air that is saturated with vapor of water or deuterium oxide.

Assignments (23)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0655 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Nov 1, 2007
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 020045/0448 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 20, 2004
From: PASSLACK, MATTHIAS; MEDENDORP, JR., NICHOLAS W.
To: FREESCALE SEMICONDUCTOR INC
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