Device and method for sharing charge
View Patent ↗A method for sharing charge between IO circuits, the method includes providing an integrated circuit that comprises multiple IO circuits, each comprising an IO pad. The method is characterized by including: determining to share a charge between multiple IO circuits; and sharing charge between the multiple IO circuits by coupling the multiple IO circuits to a shared circuit that is characterized by a state that reflects multiple iterations of sharing charge operations.
1. A method for sharing charge between IO circuits, the method comprises:
providing an integrated circuit that comprises multiple IO circuits, each IO circuit comprising:
an IO pad; and
a shared charge logic;
determining to share a charge between a first IO circuit of the multiple IO circuits and a shared circuit; and
selectively coupling a first IO pad associated with the first IO circuit to the shared circuit, wherein:
the shared circuit is operable to share charge with the first IO pad;
the shared circuit is characterized by a state that reflects multiple iterations of charge sharing operations; and
in selectively coupling the first IO pad to the shared circuit, a first shared charge logic associated with the first IO circuit operates to select the first IO pad.
2. The method according to claim 1 wherein the shared circuit comprises capacitor.
3. The method according to claim 1 wherein the multiple IO circuits belong to an integrated circuit and wherein the shared circuit comprises a large capacitor that is coupled to the integrated circuit.
4. The method according to claim 1 wherein the stage of selectively coupling the first IO pad to the shared circuit comprises coupling the first IO pad to the shared circuit via an ESD bus.
5. The method according to claim 4 further comprising coupling the first IO pad in response to a detection of an ESD event.
6. The method according to claim 1 wherein the determining comprises determining by the first shared charge logic that the first IO circuit is expected to alter a state of the first IO pad.
7. The method according to claim 1 further comprising de-coupling the first IO pad from the shared circuit.
8. The method according to claim 1 wherein the shared circuit is characterized by a state that reflects more than five chare sharing cycles.
9. A device having sharing charge capabilities, the device comprises:
a group of IO circuits, each IO circuit comprising:
an IO pad;
a shared charge logic adapted to determine to share a charge between the associated IO pad of the IO circuit and a shared circuit; and
switching circuitry adapted to selectively couple the associated IO pad to the shared circuit so as to share charge between the IO pad and the shared circuit;
wherein the shared circuit is characterized by a state that reflects multiple iterations of sharing charge operations.
10. The device according to claim 9 wherein the shared circuit is a capacitor.
11. The device according to claim 10 wherein the capacitor is coupled to an integrated circuit that comprises the multiple IO circuits.
12. The device according to claim 9 wherein the switching circuitry is coupled to the shared circuit via an ESD bus.
13. The device according to claim 12 further comprising a controller adapted to couple the two or more IO circuits to an ESD bus in response to a detection of an ESD event.
14. The device according to claim 9 wherein the shared charge logic is adapted to select the associated IO pad wherein the IO circuit is expected to alter a state of the associated IO pad.
15. The device according to claim 9 wherein the switching circuitry is adapted to de-coupling the IO pad from the shared circuit.
16. The device of claim 9 wherein the shared circuitry is characterized by a state that reflects more than five charge sharing cycles.
17. A method of claim 1 further comprising:
determining to share a charge between a second IO circuit of the multiple IO circuits, the first IO circuit, and the shared circuit; and
selectively coupling a second IO pad associated with the second IO circuit to the first IO pad and to the shared circuit, wherein a second shared charge logic associated with the second IO circuit operates to select the second IO circuit.
18. The method of claim 1 , wherein each shared charge logic comprises:
a delay unit; and
an XOR logic gate;
wherein:
a data state of the associated IO circuit is provided to an input of the delay unit, and to a first input of the XOR logic gate;
an output of the delay unit is provided to a second input of the XOR logic gate; and
an output of the XOR logic gate operates to select the associated IO circuit to be coupled to the shared circuit.
19. The device of claim 9 , wherein each shared charge logic comprises:
a delay unit; and
an XOR logic gate;
wherein:
a data state of the associated IO circuit is provided to an input of the delay unit, and to a first input of the XOR logic gate;
an output of the delay unit is provided to a second input of the XOR logic gate; and
an output of the XOR logic gate operates to select the associated IO circuit to be coupled to the shared circuit.