Memory with robust data sensing and method for sensing data
View Patent ↗A memory ( 100 ) includes first ( 116 ) and second ( 118 ) sense amplifiers, a first logic gate ( 120 ), a first three-state driver ( 130 ), and a latch ( 180 ). The first sense amplifier ( 116 ) is coupled to a first local data line and has an output terminal for providing a signal indicative of a state of a selected memory cell on the first local data line. The second sense amplifier ( 118 ) is coupled to a second local data line and has an output terminal for providing a signal indicative of a state of a selected memory cell on the second local data line. The first three-state driver ( 130 ) has a data input terminal coupled to the output terminal of the first logic gate ( 120 ), a control input terminal for receiving a first select signal, and an output terminal coupled to a global data line. The latch ( 180 ) has an input/output terminal coupled to the global data line ( 170 ).
1. A memory comprising:
a first sense amplifier coupled to a first local data line having an output terminal for providing a signal indicative of a state of a selected memory cell on said first local data line;
a second sense amplifier coupled to a second local data line having an output terminal for providing a signal indicative of a state of a selected memory cell on said second local data line;
a first logic gate having a first input terminal coupled to said output terminal of said first sense amplifier, a second input terminal coupled to said output terminal of said second sense amplifier, and an output terminal;
a first three-state driver having a data input terminal coupled to said output terminal of said first logic gate, a control input terminal for receiving a first select signal, and an output terminal coupled to a global data line; and
a latch having an input/output terminal coupled to said global data line.
2. The memory of claim 1 further comprising first and second sense amplifier precharge circuits for respectively precharging said first and second local data lines.
3. The memory of claim 2 wherein said first and second sense amplifier precharge circuits respectively precharge said first and second local data lines to a logic high level and said first logic gate comprises a NAND gate.
4. The memory of claim 1 wherein said latch further has a first control input terminal for receiving a latch signal.
5. The memory of claim 4 wherein said first sense amplifier further has an enable input terminal for receiving a first enable signal, and said second sense amplifier further has an enable input terminal for receiving a second enable signal, and wherein the memory further comprises a control circuit that activates one of said first and second enable signals during a first portion of a memory access cycle, and said latch signal during a second portion of said memory access cycle subsequent to said first portion of said memory access cycle.
6. The memory of claim 5 wherein said latch further has a precharge input terminal for receiving a precharge signal, wherein said control circuit activates said precharge signal during a third portion of said memory access cycle prior to said first portion of said memory access cycle.
7. The memory of claim 1 further comprising:
a third sense amplifier coupled to a third local data line having an output terminal for providing a signal indicative of a state of a selected memory cell on said third local data line;
a fourth sense amplifier coupled to a fourth local data line having an output terminal for providing a signal indicative of a state of a selected memory cell on said fourth local data line;
a second logic gate having a first input terminal coupled to said output terminal of said third sense amplifier, a second input terminal coupled to said output terminal of said fourth sense amplifier, and an output terminal; and
a second three-state driver having a data input terminal coupled to said output terminal of said second logic gate, a control input terminal for receiving a first control signal, and an output terminal coupled to said global data line.
8. A memory comprising:
a first group of sectors including:
a plurality of sectors, each sector including a plurality of sense amplifiers coupled to respective local data lines, each sense amplifier having an output terminal for providing a signal indicative of a state of a selected memory cell on a corresponding local data line, and a logic gate having a plurality of input terminals coupled to corresponding output terminals of said plurality of sense amplifiers, and an output terminal;
a plurality of three-state drivers each having data input terminals coupled to said output terminal of said logic gate of a corresponding one of said plurality of sectors, a control input terminal for receiving a corresponding one of a plurality of select signals, and output terminals coupled to a global data line; and
a latch having an input/output terminal coupled to said global data line.
9. The memory of claim 8 wherein said first group of sectors further comprises a plurality of sense amplifier precharge circuits for precharging respective ones of said plurality of local data lines.
10. The memory of claim 8 wherein each sense amplifier precharge circuit precharges a respective one of said plurality of local data lines to a logic high level and said first logic gate of each of said plurality of sectors comprises a NAND gate.
11. The memory of claim 8 wherein said latch further has a control input terminal for receiving a latch signal.
12. The memory of claim 8 further comprising:
at least one further group of sectors each having an organization substantially the same as said first group of sectors and a corresponding global data line; and
a multiplexer having a plurality of input terminals coupled to corresponding global data lines of said first group of sectors and said at least one further group of sectors, a control input terminal for receiving a group select signal, and an output terminal for providing a data output signal.
13. A method for sensing data in a memory comprising the steps of:
outputting a voltage on each of a first plurality of local data lines, said voltage representative of a state of a selected memory cell in a corresponding one of a first plurality of blocks;
enabling one of a first plurality of sense amplifiers, each one of said first plurality of sense amplifiers coupled to a respective one of said first plurality of local data lines;
detecting whether said enabled one of said first plurality of sense amplifiers is driving a predetermined logic level using a first logic gate;
driving a voltage on a global data line corresponding to an output of said first logic gate; and
latching a voltage on said global data line.
14. The method of claim 13 wherein said step of detecting comprises the step of:
detecting whether said enabled one of said first plurality of sense amplifiers is driving a logic low using a NAND gate.
15. The method of claim 13 wherein said step of driving comprises the step of:
selectively driving said voltage on said global data line corresponding to an output of said first logic gate in response to a first sector select signal.
16. The method of claim 15 further comprising the step of:
outputting a voltage on each of a second plurality of local data lines, said voltage representative of a state of a selected memory cell in a corresponding one of a second plurality of blocks;
enabling one of a second plurality of sense amplifiers, each one of said second plurality of sense amplifiers coupled to a respective one of said second plurality of local data lines;
detecting whether said enabled one of said second plurality of sense amplifiers is driving a predetermined logic level using a second logic gate; and
selectively driving a voltage on said global data line corresponding to an output of said second logic gate in response to a second sector select signal.
17. The method of claim 13 further comprising the step of:
precharging each of said first plurality of local data lines to a predetermined logic level before said step of enabling.
18. The method of claim 17 further comprising the step of:
precharging each of said first plurality of bit lines to a logic high;
and wherein said step of detecting comprises the step of:
detecting whether said enabled one of said plurality of sense amplifiers is driving a logic low.
19. The method of claim 17 further comprising the step of:
performing said step of precharging during a first portion of a memory access cycle;
performing said step of enabling during a second portion of said memory access cycle subsequent to said first portion; and
performing said step of latching during a third portion of said memory access cycle subsequent to said second portion.
20. The method of claim 13 wherein said step of driving comprises the step of:
driving said voltage on said global data line corresponding to said output of said first logic gate using a three state driver that is active when a sector that includes said first plurality of blocks is active.