Methods and apparatus for simulating distributed effects
View Patent ↗In general, various embodiments of the present invention relate to systems and methods for simulating distributed effects by providing a meshing pattern ( 200 ) (e.g., a two-dimensional meshing pattern that is part of a recognition layer), applying that meshing pattern to the physical layout ( 100 ), and partitioning the physical layout into a three-dimensional netlist ( 300 ) of components derived from the unit cells defined by the meshing pattern ( 200 ), thereby modeling the parasitics within the design.
1. A method for simulating distributed effects associated with a semiconductor device that includes a first metallization, a second metallization, and an active area, the method comprising:
providing a physical layout of the semiconductor device;
providing a meshing pattern;
superimposing the meshing pattern on the physical layout;
partitioning the physical layout into unit cells in accordance with the meshing pattern;
extracting components from the unit cells, wherein the components include
a first set of series resistors that model the first metallization,
a second set of series resistors that model the second metallization, and
a set of devices between the first set of series resistors and the second set of series resistors that model the active area, wherein the set of devices include devices that correspond to a type of the semiconductor device;
forming a netlist of the components extracted from the unit cells; and
simulating electrical operation of the netlist of unit cells and determining the distributed effects associated therewith.
2. The method of claim 1 , wherein the meshing pattern is a regular two-dimensional pattern.
3. The method of claim 1 , wherein the meshing pattern is a regular array of rectangular regions.
4. The method of claim 3 , wherein the rectangular regions have a size selected in accordance with a feature size of the physical layout.
5. The method of claim 1 , wherein partitioning the physical layout into unit cells includes segmenting a core device within the physical layout.
6. The method of claim 1 , wherein partitioning the physical layout into unit cells includes fragmenting a metal layer within the physical layout.
7. The method of claim 1 , wherein partitioning the physical layout into unit cells includes collating a set of vias and a set of contacts within the physical layout.
8. The method of claim 1 , wherein the semiconductor device is a field effect transistor, and the physical layout includes a source finger and an associated drain finger, and wherein the meshing pattern is configured such that a mesh region within the meshing pattern has a width substantially equal to a distance between the source finger and the drain finger.
9. The method of claim 1 , wherein the step of providing a meshing pattern includes providing an algorithm configured to produce the meshing pattern.
10. The method of claim 1 , further including generating the meshing pattern during the step of providing the physical layout.
11. The method of claim 1 , wherein the semiconductor device is a large-area active device, and wherein the set of devices include active components.
12. The method of claim 1 , wherein the semiconductor device is a transistor, and the set of devices include transistors.
13. The method of claim 1 , wherein the semiconductor device is a field effect transistor, the first metallization is a first finger of the field effect transistor corresponding to a drain metallization, the second metallization is a second finger of the field effect transistor corresponding to a source metallization, and the set of devices include field effect transistors.
14. The method of claim 1 , wherein:
partitioning the physical layout into the unit cells includes partitioning the physical layout so that a first unit cell includes a first portion of the first metallization, a first portion of the second metallization, and a first portion of the active area, and a second unit cell includes a second portion of the first metallization, a second portion of the second metallization, and a second portion of the active area; and wherein
extracting the components includes extracting the components from the first unit cell and the second unit cell so that
the first set of series resistors models the first portion of the first metallization and the second portion of the first metallization,
the second set of series resistors models the first portion of the second metallization and the second portion of the second metallization, and
the set of devices models the first portion of the active area and the second portion of the active area.
15. A system for simulating distributed effects in a semiconductor device that includes a first metallization, a second metallization, and an active area, the system comprising:
a layout module configured to provide a physical layout of the semiconductor device;
a distributed effects module configured to provide a meshing pattern, superimpose the meshing pattern on the physical layout, partition the physical layout into unit cells in accordance with the meshing pattern, extract components from the unit cells, wherein the components include a first set of series resistors that model the first metallization, a second set of series resistors that model the second metallization, and a set of devices between the first set of series resistors and the second set of series resistors that model the active area, wherein the set of devices include devices that correspond to a type of the semiconductor device, and the distributed effects module is further configured to form a netlist of the components extracted from the unit cells; and
a simulation module configured to simulate electrical operation of the netlist and determine the distributed effects associated therewith.
16. The system of claim 15 , wherein the meshing pattern is a regular array of rectangular regions.
17. The system of claim 16 , wherein the rectangular regions have a size selected in accordance with a feature size of the physical layout.
18. The system of claim 15 , wherein the distributed effects module partitions the physical layout into unit cells by segmenting a core device within the physical layout.
19. The system of claim 15 , wherein the distributed effects module partitions the physical layout into unit cells by fragmenting a metal layer within the physical layout.
20. The system of claim 15 , wherein the distributed effects module partitions the physical layout into unit cells by collating a set of vias and a set of contacts within the physical layout.
21. The system of claim 15 , wherein the semiconductor device is a large-area active device, and wherein the set of devices include active components.
22. The system of claim 15 , wherein the semiconductor device is a transistor, and the set of devices include transistors.
23. A method for generating a netlist of components associated with parasitic effects in a semiconductor device defined by a physical layout, wherein the physical layout includes a first metallization, a second metallization, and an active area, and the method comprises:
providing a meshing pattern;
breaking connectivity within diffusions defined in said physical layout in accordance with the meshing pattern;
segmenting the first metallization and the second metallization defined in said physical layout in accordance with the meshing pattern;
extracting equivalent components based on the breaking and segmenting steps, wherein the components include
a first set of series resistors that model the first metallization,
a second set of series resistors that model the second metallization, and
a set of devices between the first set of series resistors and the second set of series resistors that model the diffusions, wherein the set of devices include devices that correspond to a type of the semiconductor device; and
producing a netlist of equivalent components in accordance with the breaking connectivity step and the segmenting metallization step.
24. The method of claim 23 , wherein the physical layout includes a plurality of drawing layers, and the meshing pattern comprises an extraction layer.
25. The method of claim 23 , wherein the meshing pattern is a two-dimensional array of rectangular mesh regions.
26. The method of claim 23 , further including collating a set of vias and a set of contacts within the physical layout.
27. The method of claim 23 , wherein the semiconductor device is a large-area active device, and wherein the set of devices include active components.
28. The method of claim 23 , wherein the semiconductor device is a transistor, and the set of devices include transistors.