Noise isolation between circuit blocks in an integrated circuit chip
View Patent ↗An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation.
1. An integrated circuit, comprising:
a substrate;
a first circuit block formed in the substrate;
a second circuit block formed in the substrate;
a plurality of noise isolation regions formed between the first circuit block and the second circuit block, the plurality of noise isolation regions comprising:
a p-well block region formed in the substrate and having a first doping concentration of a p-type dopant, the p-well block region at least partially positioned between the first circuit block and the second circuit block, the p-well block region not including any active region therein;
a first guard region formed in the substrate between the p-well block region and the first circuit block, the first guard region having a second doping concentration of a p-type dopant; and
a first grounded highly doped region formed in the substrate between the first guard region and the first circuit block, the first grounded highly doped region having a third doping concentration of a p-type dopant; and
a first trench formed in the substrate between the p-well block region and the first guard region; and
wherein the second doping concentration is higher than the first doping concentration, and wherein the third doping concentration is higher than the second doping concentration.
2. The integrated circuit of claim 1 , wherein the first trench has a depth greater than that of the p-well block region and the first guard region.
3. The integrated circuit of claim 1 , further comprising:
a second guard region formed in the substrate between the p-well block region and the second circuit block, the second guard region having the second doping concentration.
4. The integrated circuit of claim 3 , further comprising:
a second grounded highly doped region formed in the substrate between the second guard region and the second circuit block, the second grounded highly doped region having the third doping concentration.
5. The integrated circuit of claim 3 , further comprising a second trench formed between the p-well block region and the second guard region.
6. The integrated circuit of claim 5 , wherein the second trench has a depth greater than that of the p-well block region and the second guard region.
7. The integrated circuit of claim 3 , wherein the first guard region and the second guard region surround the p-well block region.
8. The integrated circuit of claim 3 , wherein the first guard region and the second guard region each have a depth substantially equivalent to the depth of the p-well block region.
9. The integrated circuit of claim 1 , further comprising a dielectric layer formed over the p-well block region, the trench, the first guard region, and the first grounded highly doped region.
10. The integrated circuit of claim 9 , further comprising a conductive shield formed over the dielectric layer.
11. The integrated circuit of claim 10 , wherein the conductive shield is grounded and configured to provide additional noise isolation between the first circuit block and the second circuit block.
12. An integrated circuit, comprising:
a substrate;
a first circuit block formed in the substrate;
a second circuit block formed in the substrate;
a plurality of noise isolation regions formed between the first circuit block and the second circuit block, the plurality of noise isolation regions comprising:
a p-well block region formed in the substrate by blocking insertion of dopants in a region of the substrate between the first circuit block and the second circuit block;
at least one guard region surrounding the p-well block region;
a first grounded highly doped region formed between p-well block region and the first circuit block; and
a second grounded highly doped region formed between the p-well block region and the second circuit block;
a dielectric layer formed at least over the p-well block region; and
a grounded conductive shield formed over the dielectric layer.
13. The integrated circuit of claim 12 further comprising at least one trench formed in the substrate and bordering the guard region.
14. The integrated circuit of claim 13 , wherein the at least one trench has a depth greater than the at least one guard region.
15. The integrated circuit of claim 12 , wherein the p-well block region comprises a wall formed between the first circuit block and the second circuit block.
16. The integrated circuit of claim 12 , wherein the dielectric layer extends over the p-well block region, the at least one guard region, the first grounded highly doped region, and the second grounded highly doped region.
17. An integrated circuit, comprising:
a substrate;
a first circuit block formed in the substrate;
a second circuit block formed in the substrate;
a plurality of noise isolation regions formed between the first circuit block and the second circuit block, the plurality of noise isolation regions comprising:
a p-well block region formed in the substrate;
a first guard region formed between the p-well block and the first circuit block;
a second guard region formed between the p-well block and the second circuit block;
a first grounded highly doped region formed between the first guard region and the first circuit block; and
a second grounded highly doped region formed between the second guard region and the second circuit block;
a first trench formed in the substrate between the p-well block region and the first grounded highly dope region;
a second trench formed in the substrate between the p-well block region and the second grounded highly dope region;
a dielectric layer formed at least over the p-well block region, the first trench, and the second trench; and
a grounded conductive shield formed over the dielectric layer.
18. The integrated circuit of claim 17 , wherein the first and second guard regions are integrally formed as a ring surrounding the p-well block region.
19. The integrated circuit of claim 17 , wherein the p-well block region does not including any active regions therein.
20. The integrated circuit of claim 19 , wherein the p-well block region has a first doping concentration of a p-type dopant, wherein the first guard region has a second doping concentration of a p-type dopant greater than the first doping concentration, and wherein first grounded highly doped region has a third doping concentration of a p-type dopant greater than the second doping concentration.