Patent Assignment
Reel/Frame 037357/0744
Patent Release
Recorded: 2015-12-21
Pages: 19
Assignor
CITIBANK, N.A., AS COLLATERAL AGENT
Executed: 2015-12-07
Assignee
FREESCALE SEMICONDUCTOR, INC.
6501 WILLIAM CANNON DRIVE WEST, AUSTIN, TEXAS, 78735
Covered Properties
(189)
Suppression of Redundant Cache Status Updates
Application:
13/732,533 →
Publication:
US 2014/0189244
System for Reducing Power Consumption of Electronic Circuit
Patent:
8,527,935 →
Application:
13/735,049 →
System for Managing Uplink Quality of Service (Qos) in Cellular Network
Bose-Chaudhuri-Hocquenghem (Bch) Decoder
Configurable Circuit and Mesh Structure for Integrated Circuit
Patent:
8,645,892 →
Application:
13/735,053 →
Integrated Circuit Design Verification System
Patent:
8,645,897 →
Application:
13/735,054 →
Memory Having Improved Reliability for Certain Data Types
Memory Using Voltage to Improve Reliability for Certain Data Types
Schmitt Trigger Circuit with Near Rail-to-Rail Hysteresis
Patent:
8,736,333 →
Application:
13/736,440 →
Method and Apparatus for Testing a Random Number Generator Tester
Bus Signal Encoded with Data and Clock Signals
Methods And Systems For Pushing Dirty Linefill Buffer Contents To External Bus Upon Linefill Request Failures
Transmission System
Multiport Memory with Matching Address and Data Line Control
Multiport Memory with Matching Address Control
Microelectronic Assembly Having a Heat Spreader for a Plurality of Die
Digital to Analog Converter with Current Steering Source for Reduced Glitch Energy Error
Patent:
8,723,712 →
Application:
13/742,532 →
Reducing Output Voltage Ripple of Power Supplies
Capacitor Charging Circuit with Low Sub-Threshold Transistor Leakage Current
Well-Biasing Circuit for Integrated Circuit
Dma-Assisted Irregular Sampling Sequences
Systems and Methods for Reduced Coupling Between Digital Signal Lines
Systems and Methods for Adaptive Soft Programming for Non-Volatile Memory Using Temperature Sensor
Devices and Methods for Configuring Conductive Elements for a Semiconductor Package
Patent:
8,754,518 →
Application:
13/746,874 →
Vector Comparator System for Finding a Peak Number
Flash Memory with Bias Voltage for Word Line/Row Driver
Patent:
8,737,137 →
Application:
13/747,088 →
Die Edge Sealing Structures and Related Fabrication Methods
Dynamic Detection Method for Latent Slow-to-Erase Bit for High Performance and High Reliability Flash Memory
Manufacturing Methods for Laterally Diffused Metal Oxide Semiconductor Devices
Semiconductor Device with Enhanced 3D Resurf
Systems and Method for Gyroscope Calibration
Power Supply for Integrated Circuit
Sigma-Delta Modulator with Trimmed Reference Voltage for Quantizer
Methods and Structures for Dynamically Calibrating Reference Voltage
Application:
13/748,798 →
Publication:
US 2014/0203794
Method of Making a Non-Volatile Memory (Nvm) Cell Structure
Variable Delay and Setup Time Flip-Flop
Area-Efficient High Voltage Bipolar-Based Esd Protection Targeting Narrow Design Windows
Method of Forming an Integrated Circuit Having Varying Substrate Depth
Layout-Optimized Random Mask Distribution System and Method
Cryptographic Key Derivation Device and Method Therefor
Electronic Device Module with Integrated Antenna Structure, and Related Manufacturing Method
Programming a Split Gate Bit Cell
Microelectromechanical System Devices Having Crack Resistant Membrane Structures and Methods for the Fabrication Thereof
Non-Volatile Memory Cells Having Carbon Impurities and Related Manufacturing Methods
Application:
13/753,047 →
Publication:
US 2014/0209995
Relaxation Oscillator with Self-Biased Comparator
Semiconducitive Catechol Group Encapsulant Adhesion Promoter for a Packaged Electronic Device
Amplitude Loop Control for Oscillators
Dynamic Healing Of Non-Volatile Memory Cells
Method for Formng a Semiconductor Device Assembly Having a Heat Spreader
Nonvolatile Memory Bitcell
Application:
13/756,248 →
Publication:
US 2014/0209988
Lead Frame Array Package with Flip Chip Die Attach
Patent:
8,710,636 →
Application:
13/758,263 →
Write Transaction Interpretation for Interrupt Assertion
Memory Error Management System
Voltage Scale-Down Circuit
Electrostatic Discharge Circuit
System and Method for Maintaining Packet Order in an Ordered Data Stream
Stiction Resistant Mems Device and Method of Operation
Methods for Fabricating Bipolar Transistors with Improved Gain
System and Method for Scan Chain Re-Ordering
Embedded Nvm in a Hkmg Process
Pressure Level Adjustment in a Cavity of a Semiconductor Die
Application:
13/764,246 →
Publication:
US 2014/0225206
Methods Relating to the Fabrication of Devices Having Conductive Substrate Vias with Catch-Pad Etch-Stops
Esd Protection with Integrated Ldmos Triggering Junction
Fine Grain Voltage Scaling of Back Biasing
Patent:
8,710,906 →
Application:
13/764,946 →
Methods and Structures for Reducing Stress on Die Assembly
Methods Relating to Intermetallic Testing of Bond Integrity Between Bond Pads and Copper-Containing Bond Wires
Patent:
8,741,666 →
Application:
13/766,445 →
Solar Powered Ic Chip
Timing Margins for On-chip Variations from Sensitivity Data
Patent:
8,656,331 →
Application:
13/767,064 →
Circuit and Method for Voltage Equalization in Large Batteries
Circuit and Method for Battery Equalization
Spring System for Mems Device
Application:
13/770,224 →
Publication:
US 2014/0230549
Methods for Forming Electrostatic Discharge Protection Clamps with Increased Current Capabilities
Level Shifter Circuit
Patent:
8,723,582 →
Application:
13/771,025 →
Semiconductor Device and Related Fabrication Methods
Low Power Quantizer for Analog to Digital Converter
Semiconductor Packages with Low Stand-Off Interconnections Between Chips
Application:
13/773,578 →
Publication:
US 2014/0231977
Semiconductor Package with Inner and Outer Leads
Semiconductor Grid Array Package
Transition Control for a Hybrid Switched-Mode Power Supply (Smps)
Thin Beam Deposited Fuse
Methods And Systems For Address Mapping Between Host And Expansion Devices Within System-In-Package (SiP) Solutions
Methods And Systems For Interconnecting Host And Expansion Devices Within System-In-Package (SiP) Solutions
Robust Sector Id Scheme for Tracking Dead Sectors to Automate Search and Copydown
Method for Bonding Semiconductor Devices
Application:
13/777,715 →
Publication:
US 2014/0242777
Mishfet and Schottky Device Integration
Scan Diagnosis Analysis Using Callout Clustering
Application:
13/778,546 →
Publication:
US 2014/0245066
Data Acquisition System
Patent:
8,643,526 →
Application:
13/779,751 →
Split Gate Non-Volatile Memory (Nvm) Cell and Method Therefor
Synchronous Multiple Port Memory with Asynchronous Ports
Non-Volatile Memory (Nvm) and Logic Integration
Non-Volatile Memory (Nvm) and Logic Integration
Sense Amplifier Voltage Regulator
Microelectromechanical System Devices Having Through Substrate Vias and Methods for the Fabrication Thereof
Resurf Semiconductor Device Charge Balancing
Methods of Making Logic Transistors and Non-Volatile Memory Cells
Packaged Semiconductor Device
System for Reducing Electromagnetic Induction Interference
Systems and Methods for Indicating That an Interface Is Being Touched
Application:
13/787,290 →
Publication:
US 2014/0253489
Temperature-Based Adaptive Erase or Program Parallelism
Prioritized Design for Manufacturing Virtualization with Design Rule Checking Filtering
Test Control Point Insertion and X-Bounding for Logic Built-in Self-Test (Lbist) Using Observation Circuitry
Robust Memory Start-Up Using Clock Counter
Semiconductor Dies Having Substrate Shunts and Related Fabrication Methods
Programmable Direct Memory Access Channels
Lead Frame for Semiconductor Package
Application:
13/789,660 →
Publication:
US 2014/0252575
System and Method for Dynamically Migrating Stash Transactions
Patent:
8,671,232 →
Application:
13/789,661 →
Integration Technique Using Thermal Oxide Select Gate Dielectric for Select Gate and Replacement Gate for Logic
Integration Technique Using Thermal Oxide Select Gate Dielectric for Select Gate and Apartial Replacement Gate for Logic
Integrating Formation of a Logic Transistor and a Non-Volatile Memory Cell Using a Partial Replacement Gate Technique
Patent:
8,741,719 →
Application:
13/790,014 →
Integrating Formation of a Replacement Gate Transistor and a Non-Volatile Memory Cell Having Thin Film Storage
Patent:
8,716,089 →
Application:
13/790,225 →
Gate Security Feature
System and Method for Monitoring a Gyroscope
Symmetrical Data Replication For Failure Management In Non-Volatile Memory Systems
Application:
13/791,012 →
Publication:
US 2014/0258792
System and Method for Reducing Offset Variation in Multifunction Sensor Devices
System and Method for Monitoring an Accelerometer
Semiconductor Device with Integrated Electrostatic Discharge (ESD) Clamp
Semiconductor Device with Increased Safe Operating Area
Multiplier Circuit
Mold Chase
Wire Bonding Apparatus and Method
Application:
13/794,836 →
Publication:
US 2014/0263584
Lead Frame for Semiconductor Package with Enhanced Stress Relief
Mcu-Based Compensation and Calibration for Mems Devices
Multiport Memory with Matching Address Control
Brace for Bond Wire
Patent:
8,680,660 →
Application:
13/798,052 →
Resolution Programmable Dynamic Ir-Drop Sensor with Peak Ir-Drop Tracking Abilities
Angular Rate Sensor Having Multiple Axis Sensing Capability
Semiconductor Device
Semiconductor Device Assembly Having a Heat Spreader
Patent:
8,754,521 →
Application:
13/799,031 →
Wireless Charging Systems, Devices, and Methods
Deep Trench Isolation
System and Method for Ordering Packet Transfers in a Data Processor
Noise Isolation Between Circuit Blocks in an Integrated Circuit Chip
Electronic Circuit, Safety Critical System, and Method for Providing a Reset Signal
Integrated Circuit Device, Data Storage Array System and Method Therefor
Clock Circuit and Method for Providing an Electronic Device with an Adjustable Clock Signal
System and Method for Outputting Image Data Including Safety Relevant Information
Application:
13/810,746 →
Publication:
US 2013/0120437
Method for Optimising Cell Variant Selection Within a Design Process for an Integrated Circuit Device
Latch Circuit, Flip-Flop Circuit and Frequency Divider
Multi-Core Processor and Method of Power Management of a Multi-Core Processor
Application:
13/811,942 →
Publication:
US 2013/0124890
Apparatus and Method for Reducing Processor Latency
Application:
13/812,168 →
Publication:
US 2013/0124800
Electronic Circuit and Method for State Retention Power Gating
Push-Push Oscillator Circuit
Optimization Method for Compiler, Optimizer for a Compiler and Storage Medium Storing Optimizing Code
Memory Management Unit for a Microprocessor System, Microprocessor System and Method for Managing Memory
Video Processing System and Method for Parallel Processing of Video Data
Application:
13/818,480 →
Publication:
US 2013/0148717
Group-III Nitride Epitaxial Layer on Silicon Substrate
Application:
13/821,070 →
Publication:
US 2013/0175671
Low-Voltage Exit Detector, Error Detector, Low-Voltage Safe Controller, Brown-Out Detection Method, and Brown-Out Self-Healing Method
Application:
13/824,537 →
Publication:
US 2013/0181696
Integrated Circuit Device, Wireless Communication Unit and Method of Manufacture Therefor
Method and Device for Detecting a Race Condition
Computer Systems and Methods with Resource Transfer Hint Instruction
Transistor with Charge Enhanced Field Plate Structure and Method
Built-In Self Test (Bist) with Clock Control
Application:
13/826,347 →
Publication:
US 2014/0281717
Memory with Power Savings for Unnecessary Reads
Non-Volatile Memory (Nvm) with Word Line Driver/Decoder Using a Charge Pump Voltage
Data Processor Device for Handling a Watchpoint and Method Thereof
Voltage Regulator with Current Limiter
Microelectromechanical System Devices Having Through Substrate Vias and Methods for the Fabrication Thereof
Methods and Apparatus for Sensing Motion of a Portable Container and Providing Human Perceptible Indicia Based on the Sensed Motion
Stacked Microelectronic Packages Having Sidewall Conductors and Methods for the Fabrication Thereof
Address Calculation for Received Data
Application:
13/830,701 →
Publication:
US 2014/0281367
Dual Supply Level Shifter Circuits
Method and Apparatus for Detecting a Collision Between Multiple Threads of Execution for Accessing a Memory Array
Method and Apparatus for reducing the number of speculative accesses to a memory array
Multiple Axis Rate Sensor
Task Scheduling Method and Apparatus
Negative Charge Pump Regulation
Method and Apparatus for Sensing On-Chip Characteristics
Patent:
8,766,703 →
Application:
13/835,690 →
Application of Normally Closed Power Semiconductor Devices
Compensated Hysteresis Circuit
Method for Provisioning Decoupling Capacitance in an Integrated Circuit
Non-Volatile Memory (Nvm) with Block-Size-Aware Program/Erase
System and Method for Assigning Memory Access Transfers Between Communication Channels
System and Method for Improved Mems Oscillator Startup
Method and Device for Handling Data Values
Method and Device for Generating an Exception
System and Method for Transferring Data Between Components of a Data Processor
Method and Device Implementing Execute-Only Memory Protection
Continuous Run-Time Integrity Checking for Virtual Memory
System and Method for Multicore Processing
Thread-Suspending Execution Barrier
Application:
13/843,179 →
Publication:
US 2014/0282564
Power Monitoring Circuitry
Helix Substrate and Three-Dimensional Package with Same
Inhibiting Propagation of Surface Cracks in a Mems Device
Methods and Systems for Selectively Forming Metal Layers on Lead Frames After Die Attachment
Solar Powered Ic Chip
Patent:
8,778,704 →
Application:
13/849,543 →
System for Managing Configuration Updates in Cluster of Computational Devices
Application:
13/853,061 →
Publication:
US 2014/0297774
Voltage Switching Circuitry, Integrated Device and Integrated Circuit, and Method of Voltage Switching
Two-photon laser-assisted device alteration in silicon integrated-circuits
Application:
61/804,696 →
Synchronized Pulsed LADA for the simultaneous Acquisition of Timing Diagrams and Laser-Induced Upsets
Application:
61/806,803 →
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jan 2, 2013
From: GRAYSON, BRIAN C.; BURGESS, DAVID P.; WILSON, PETER J.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029552/0583 →
Assignment of Assignor's Interest
Jan 8, 2013
From: VERMA, CHETAN; ROY, AMIT; TAYAL, VIJAY
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029581/0679 →
Assignment of Assignor's Interest
Jan 8, 2013
From: TERCARIOL, WALTER L.; SAEZ, RICHARD TITOV LARA
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029587/0948 →
Assignment of Assignor's Interest
Jan 8, 2013
From: RUSSELL, ANDREW C.; RAMARAJU, RAVINDRARAJ
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029586/0278 →
Assignment of Assignor's Interest
Jan 8, 2013
From: RUSSELL, ANDREW C.; RAMARAJU, RAVINDRARAJ
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029586/0175 →
Assignment of Assignor's Interest
Jan 8, 2013
From: TANEJA, MUKESH
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029582/0093 →
Assignment of Assignor's Interest
Jan 8, 2013
From: GUPTA, VISHAL; DODEJA, PUNEET; SINGH, HANS RAJ
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029581/0722 →
Assignment of Assignor's Interest
Jan 8, 2013
From: ., NANDINI; GUPTA, GAURAV; SRIVASTAVA, ROHIT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029581/0717 →
Assignment of Assignor's Interest
Jan 8, 2013
From: SRIVASTAVA, ANKUSH
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029581/0714 →
Assignment of Assignor's Interest
Jan 11, 2013
From: PELLEY, PERRY H.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029616/0058 →
Assignment of Assignor's Interest
Jan 11, 2013
From: BROCKER, MATTHEW W.; CORNELIUS, STEVEN E.; TKACIK, THOMAS E.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029615/0815 →
Assignment of Assignor's Interest
Jan 14, 2013
From: PHO, QUYEN
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029620/0599 →
Assignment of Assignor's Interest
Jan 14, 2013
From: PELLEY, PERRY H.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029623/0727 →
Assignment of Assignor's Interest
Jan 14, 2013
From: PELLEY, PERRY H.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029623/0689 →
Assignment of Assignor's Interest
Jan 14, 2013
From: PELLEY, PERRY H.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029623/0537 →
Assignment of Assignor's Interest
Jan 15, 2013
From: STEPHENS, TAB A.; MCSHANE, MICHAEL B.; PELLEY, PERRY H.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029630/0825 →
Assignment of Assignor's Interest
Jan 16, 2013
From: TERCARIOL, WALTER LUIS; SAEZ, RICHARD TITOV LARA; SALVARANI, ALFREDO; KICKHOFEL, REMERSON STEIN
To: FREESCALE SEMINCONDUCTOR, INC.
Reel/Frame 029638/0066 →
Assignment of Assignor's Interest
Jan 16, 2013
From: KABIR, MOHAMMAD NIZAM U.; BRASWELL, BRANDT; GARRITY, DOUGLAS A.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029637/0980 →
Assignment of Assignor's Interest
Jan 17, 2013
From: SINHA, ANAND KUMAR; WADHWA, SANJAY K.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029644/0823 →
Security Agreement
Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0725 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0704 →
Assignment and Assumption of Security Interest in Patents
Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
Assignment and Assumption of Security Interest in Patents
Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
Security Agreement Supplement
Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →