Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
View Patent ↗A stacked microelectronic package can comprise a package body having an external vertical package sidewall, a plurality of microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the external vertical package sidewall. A cavity is formed on an external surface of the package body between a first one of the package edge conductors and a second one of the package edge conductors. Electrically conductive material is in the cavity and in electrical contact with a first and a second one of the package edge conductors, wherein the conductive material in the cavity is within planform dimensions of the microelectronic package.
1. A stacked microelectronic package, comprising:
a molded package body having an external vertical package sidewall;
a plurality of singulated microelectronic devices embedded within the molded package body
package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the external vertical package sidewall;
a cavity formed in an external surface of the molded package body between a first one of the package edge conductors and a second one of the package edge conductors; and
electrically conductive material in the cavity and in electrical contact with a first and a second one of the package edge conductors, wherein the conductive material in the cavity is within planform dimensions of the microelectronic package and sidewalls of the cavity cover all side edges of the electrically conductive material.
2. A stacked microelectronic package according to claim 1 wherein the package edge conductors are formed to electrically couple the plurality of microelectronic devices embedded within the molded package body.
3. A stacked microelectronic package according to claim 1 wherein the plurality of microelectronic devices comprises a first microelectronic device and a second microelectronic device located in different levels of the molded package body, and wherein the package edge conductors are formed to electrically couple the first microelectronic device to the second microelectronic device.
4. A stacked microelectronic package according to claim 3 wherein the cavity is formed in a step configuration that includes a run portion over a major surface of one of the levels of the molded package body, the run portion extending between and in contact with the external vertical package sidewall of a first level of the different levels and the external vertical package sidewall of a second level of the different levels.
5. A stacked microelectronic package according to claim 1 wherein a portion of the first and second one of the package edge conductors form part of the cavity.
6. A stacked microelectronic package according to claim 5 wherein the cavity extends beyond at least one of the first and second one of the package edge conductors.
7. A stacked microelectronic package according to claim 5 wherein the cavity extends to an intermediate location over at least one of the first and second one of the package edge conductors.
8. A stacked microelectronic package, comprising:
a molded package body having an external vertical package sidewall;
a first singulated microelectronic device embedded within a first level of the molded package body;
a second singulated microelectronic device embedded within a second level of the molded package body;
a first package edge conductor electrically coupled to the first microelectronic device and extending to the external vertical package sidewall, and a second package edge conductor electrically coupled to the second microelectronic device and extending to the external vertical package sidewall;
a cavity formed in an external surface of the molded package body between the first package edge conductor and the second package edge conductor; and
electrically conductive material in the cavity and in electrical contact with the first and second package edge conductors, wherein sidewalls of the cavity overlap all side edges of the electrically conductive material.
9. A stacked microelectronic package according to claim 8 wherein the first and second package edge conductors are formed to electrically couple the first and second microelectronic devices embedded within the molded package body.
10. A stacked microelectronic package according to claim 3 wherein the cavity is formed in a step configuration that includes a run portion over a major surface of one of the levels of the molded package body, the run portion extending between and in contact with the external vertical package sidewall of a first level of the different levels and the external vertical package sidewall of a second level of the different levels.
11. A stacked microelectronic package, comprising:
a molded package body having an external vertical package sidewall, a plurality of singulated microelectronic devices embedded within the molded package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the external vertical package sidewall;
a cavity in an external surface of the molded package body between a first one of the package edge conductors and a second one of the package edge conductors, wherein the cavity is filled with electrically conductive material and top, bottom and side edges of the electrically conductive material are covered by the cavity.
12. A stacked microelectronic package as claimed in claim 11 wherein the first and second one of the package edge conductors are formed to electrically couple the plurality of microelectronic devices embedded within the molded package body.
13. A stacked microelectronic package as claimed in claim 11 wherein the plurality of microelectronic devices comprises a first microelectronic device and a second microelectronic device located in different levels of the molded package body, and wherein the first and second one of the package edge conductors are formed to electrically couple the first microelectronic device to the second microelectronic device.
14. A stacked microelectronic package as claimed in claim 11 wherein the cavity is formed between the first and second one of the package edge conductors and the conductive material is in contact with the first and second ones of the package edge conductors.
15. A stacked microelectronic package as claimed in claim 11 wherein the cavity is formed by removing a portion of the first and second one of the package edge conductors.
16. A stacked microelectronic package as claimed in claim 15 wherein the cavity is formed by extending the cavity beyond at least one of the first and second one of the package edge conductors.
17. A stacked microelectronic package as claimed in claim 15 wherein the cavity is formed by extending the cavity to an intermediate location over at least one of the first and second one of the package edge conductors.
18. A stacked microelectronic package as claimed in claim 13 wherein the cavity is formed in a step configuration that includes a run portion over a major surface of one of the levels of the molded package body, the run portion extending between and in contact with the external vertical package sidewall of a first level of the different levels and the external vertical package sidewall of a second level of the different levels.
19. A stacked microelectronic package as claimed in claim 18 wherein the conductive material in the cavity is within planform dimensions of the microelectronic package.
20. A stacked microelectronic package as claimed in claim 11 wherein the conductive material comprises one of a group consisting of: an electrically conductive adhesive, conductive polymer, a polymer filled with conductive particles, a metal alloy, metal coated organic particles, metal coated ceramic particles, solder paste, solder-filled adhesive, nanoparticle-filled ink, a metal-containing adhesive, a metal-containing epoxies, electrically-conductive pastes, indium, and bismuth.