Memory using voltage to improve reliability for certain data types
View Patent ↗A method for minimizing soft error rates within caches by configuring a cache with a certain way which is more resistant to soft errors and then using this way to store modified data. In certain embodiments, the memory is made more soft error resistant by increasing a voltage across bitcells of the cache.
1. A memory system comprising:
a memory array, the memory array comprising a plurality of sections, each of the plurality of sections being individually configurable to operate in a more error resistant mode of operation and a less error resistant mode of operation;
a memory controller, the memory controller determining whether data to be written to the memory array comprises modified information, the memory controller storing the modified information to a section operating in the more error resistant mode of operation; and,
wherein the more error resistant mode of operation comprises providing a first voltage across at least one of the plurality of sections of the memory array and the less error resistant mode of operation comprises providing a second voltage across at least another of the plurality of sections of the memory array.
2. The memory system of claim 1 wherein:
at least one other of the sections is operating in the less error resistant mode of operation; and
the memory controller stores unmodified information to the at least one other of the sections.
3. The memory system of claim 1 wherein:
the less error resistant mode of operation corresponds to a drowsy mode of operation;
the more error resistant mode of operation corresponds to a drowsy disabled mode of operation;
the drowsy mode of operation comprises providing a first voltage across at least one of the plurality of sections of the memory array; and
the drowsy disabled mode of operation comprises providing a second voltage across at least another of the plurality of sections of the memory array.
4. The memory system of claim 3 further comprising:
a drowsy circuit coupled to the memory array, the drowsy circuit causing the first voltage to be applied across bitcells within the at least one of the plurality of sections of the memory array and the second voltage to be applied across bitcells within the at least another of the plurality of sections of the memory array.
5. The memory system of claim 4 wherein:
each of the at least one of the plurality of sections of the memory array and the at least another of the plurality of sections of the memory array are coupled to respective drowsy circuits.
6. The memory system of claim 1 wherein: the less error resistant mode of operation comprises operating at least one of the plurality of sections of the memory array at a lower voltage; and, the more error resistant mode of operation comprises operating another of the plurality of sections of the memory array at a higher voltage.
7. The memory system of claim 6 further comprising:
a voltage multiplexer circuit coupled to the memory array, the voltage multiplexer circuit causing the first voltage to be applied to the at least one of the plurality of sections of the memory array and the second voltage to be applied to the at least another of the plurality of sections of the memory array.
8. The memory system of claim 1 wherein:
the memory system is a cache of a processor.
9. A method for improving error resilience in a memory array comprising a plurality of sections comprising:
storing modified information to one of the plurality of sections;
individually configuring each of the plurality of sections to operate in a more error resistant mode of operation and a less error resistant mode of operation;
determining whether data to be written to the memory array comprises modified information;
storing the modified information to a section operating in the more error resistant mode of operation;
wherein the more error resistant mode of operation comprises providing a first voltage across at least one of the plurality of sections of the memory array and the less error resistant mode of operation comprises providing a second voltage across at least another of the plurality of sections of the memory array.
10. The method of claim 9 wherein:
at least one other of the sections is operating in the less error resistant mode of operation; and,
the memory controller stores unmodified information to the at least one other of the sections.
11. The method of claim 9 wherein:
the less error resistant mode of operation corresponds to a drowsy mode of operation;
the more error resistant mode of operation corresponds to a drowsy disabled mode of operation;
the drowsy mode of operation comprises providing a first voltage across at least one of the plurality of sections of the memory array; and
the drowsy disabled mode of operation comprises providing a second voltage across at least another of the plurality of sections of the memory array.
12. The method of claim 11 wherein:
a drowsy circuit is coupled to the memory array, the drowsy circuit causing the first voltage to be applied across bitcells within the at least one of the plurality of sections of the memory array and the second voltage to be applied across bitcells within the at least another of the plurality of sections of the memory array.
13. The method of claim 12 wherein:
each of the at least one of the plurality of sections of the memory array and the at least another of the plurality of sections of the memory array are coupled to respective drowsy circuits.
14. The method of claim 9 wherein:
the less error resistant mode of operation comprises operating at least one of the plurality of sections of the memory array at a lower voltage; and,
the more error resistant mode of operation comprises operating another of the plurality of sections of the memory array at a higher voltage.
15. The method of claim 14 further comprising:
causing the first voltage to be applied to the at least one of the plurality of sections of the memory array and the second voltage to be applied to the at least another of the plurality of sections of the memory array.
16. The method of claim 9 wherein:
the memory array is a cache of a processor.
17. A memory comprising:
a first plurality of bitcells and a second plurality of bitcells, each of the first plurality of bitcells and the second plurality of bitcells being individually configurable to operate in a more error resistant mode of operation and a less error resistant mode of operation;
storing modified data only in the more error resistant plurality of bitcells;
wherein the voltage across the first plurality of bitcells is greater than the voltage across the second plurality of bitcells.