Data acquisition system
View Patent ↗A data acquisition system for converting an analog input signal to a digital output signal includes a programmable gain amplifier (PGA), an analog to digital converter (ADC), and an averaging module. The PGA generates first and second amplified signals during respective first and second conversion cycles. The first and second amplified signals include respective first and second amplified input signals and first and second sets of offset and noise signals. The first and second amplified input signals have the same polarities, and the first and second sets of offset and noise signals have opposite polarities. The ADC generates first and second digital samples corresponding to the first and second amplified signals respectively and the averaging module averages the first and second digital samples to eliminate the first and second sets of offset and noise signals from the digital output signal.
1. A system for converting an analog input signal to a digital output signal in two or more analog-to-digital conversion cycles, the system comprising:
a programmable gain amplifier (PGA), comprising:
a first switch, that receives the analog input signal and transmits the analog input signal, during a sampling phase of a first analog-to-digital conversion cycle, and receives and switches a polarity of the analog input signal and transmits an inverted analog input signal, during a sampling phase of a second analog-to-digital conversion cycle, wherein the first and second analog-to-digital conversion cycles are consecutive conversion cycles;
a first amplifier, connected to the first switch, that receives the analog input signal and generates a first amplified signal, during the sampling phase of the first analog-to-digital conversion cycle, wherein the first amplified signal comprises a first amplified input signal and a first set of offset and noise signals, and receives the inverted analog input signal and generates a second amplified signal, during the sampling phase of the second analog-to-digital conversion cycle, wherein the second amplified signal comprises a second amplified input signal and a second set of offset and noise signals, and wherein the first and second amplified input signals have opposite polarities, and the first and second sets of offset and noise signals have the same polarity; and
a second switch, connected to the first amplifier, that receives and transmits the first amplified signal, during the sampling phase of the first analog-to-digital conversion cycle, and receives and switches a polarity of the second amplified signal, during the sampling phase of the second analog-to-digital conversion cycle, wherein the first and second amplified input signals have the same polarity, and the first and second sets of offset and noise signals have opposite polarities;
an analog-to-digital converter (ADC), connected to the second switch, that samples the first and second amplified signals, to generate first and second digital samples during conversion phases of the first and second analog-to-digital conversion cycles, respectively; and
an averaging module, connected to the ADC, that receives and averages the first and second digital samples to generate the digital output signal, wherein the averaging module eliminates the first and second sets of offset and noise signals from the digital output signal.
2. The system of claim 1 , wherein the PGA further comprises a second amplifier, connected between the second switch and the ADC, wherein the second amplifier buffers the first and second amplified signals.
3. The system of claim 1 , further comprising a control signal generator, connected to the first and second switches for providing a first control signal thereto, and to the ADC for providing a second control signal thereto.
4. The system of claim 3 , wherein the first switch switches the polarity of the analog input signal to generate the inverted analog input signal based on the first control signal, and the second switch switches the polarity of the second amplified signal based on the first control signal.
5. The system of claim 3 , further comprising a clock source, connected to the control signal generator, wherein the control signal generator generates the first and second control signals based on the clock source, and synchronizes the switching of the first control signal with the first and second analog-to-digital conversion cycles.
6. The system of claim 3 , wherein the control signal generator comprises at least one of a finite state machine and a digital counter.
7. The system of claim 1 , wherein the averaging module comprises at least one of an averaging filter and a combination of a digital adder and a divider circuit.
8. The system of claim 1 , wherein the first and second switches each comprise an analog multiplexer.
9. A system for converting an analog input signal to a digital output signal in two or more analog-to-digital conversion cycles, the system comprising:
a control signal generator that generates first and second control signals;
a programmable gain amplifier (PGA), comprising:
a first switch, connected to the control signal generator, wherein the first switch receives and transmits the analog input signal based on the first control signal, during a sampling phase of a first analog-to-digital conversion cycle, and receives and switches the polarity of the analog input signal to transmit an inverted analog input signal based on the first control signal during a sampling phase of a second analog-to-digital conversion cycle, wherein the first and second analog-to-digital conversion cycles are consecutive conversion cycles;
a first amplifier, connected to the first switch, wherein the first amplifier receives the analog input signal and generates a first amplified signal during the sampling phase of the first analog-to-digital conversion cycle, wherein the first amplified signal comprises a first amplified input signal and a first set of offset and noise signals, and wherein the first amplifier receives the inverted analog input signal and generates a second amplified signal during the sampling phase of the second analog-to-digital conversion cycle, wherein the second amplified signal comprises a second amplified input signal and a second set of offset and noise signals, and wherein the first and second amplified input signals have opposite polarities and the first and second sets of offset and noise signals have the same polarity; and
a second switch, connected to the first amplifier and the control signal generator, wherein the second switch receives and transmits the first amplified signal based on the first control signal during the sampling phase of the first analog-to-digital conversion cycle, and receives and switches the polarity of the second amplified signal based on the first control signal during the sampling phase of the second analog-to-digital conversion cycle, wherein the first and second amplified input signals have the same polarity, and the first and second sets of offset and noise signals have opposite polarities;
an analog-to-digital converter (ADC), connected to the second switch, wherein the ADC samples the first and second amplified signals to generate first and second digital samples during conversion phases of the first and second analog-to-digital conversion cycles, respectively; and
an averaging module, connected to the ADC, that receives and averages the first and second digital samples to generate the digital output signal, wherein the averaging module eliminates the first and second sets of offset and noise signals from the digital output signal.
10. The system of claim 9 , wherein the PGA further comprises a second amplifier, connected between the second switch and the ADC, wherein the second amplifier buffers the first and second amplified signals.
11. The system of claim 9 , further comprising a clock source, connected to the control signal generator, wherein the control signal generator generates the first and second control signals based on the clock source, and synchronizes the switching of the first control signal with the first and second analog-to-digital conversion cycles.
12. The system of claim 9 , wherein the control signal generator comprises at least one of a finite state machine and a digital counter.
13. The system of claim 9 , wherein the averaging module comprises at least one of an averaging filter, and a combination of a digital adder and divider circuit.
14. The system of claim 9 , wherein the first and second switches each comprise an analog multiplexer.
15. A data acquisition system, comprising:
a control signal generator that generates first and second control signals;
a programmable gain amplifier (PGA), comprising:
a first switch, connected to the control signal generator, wherein the first switch receives and transmits an analog input signal based on the first control signal during a sampling phase of a first analog-to-digital conversion cycle, and wherein the first switch receives and switches the polarity of the analog input signal to transmit an inverted analog input signal based on the first control signal during a sampling phase of a second analog-to-digital conversion cycle, wherein the first and second analog-to-digital conversion cycles are consecutive conversion cycles;
a first amplifier, connected to the first switch, wherein the first amplifier receives the analog input signal and generates a first amplified signal during the sampling phase of the first analog-to-digital conversion cycle, wherein the first amplified signal comprises a first amplified input signal and a first set of offset and noise signals, and wherein the first amplifier receives the inverted analog input signal and generates a second amplified signal during the sampling phase of the second analog-to-digital conversion cycle, wherein the second amplified signal comprises a second amplified input signal and a second set of offset and noise signals, and wherein the first and second amplified input signals have opposite polarities, and the first and second sets of offset and noise signals have the same polarity; and
a second switch, connected to the first amplifier and the control signal generator, wherein the second switch receives and transmits the first amplified signal based on the first control signal during the sampling phase of the first analog-to-digital conversion cycle, and receives and switches a polarity of the second amplified signal based on the first control signal during the sampling phase of the second analog-to-digital conversion cycle, wherein the first and second amplified input signals have the same polarity, and the first and second sets of offset and noise signals have opposite polarities;
an analog-to-digital converter (ADC), connected to the second switch, wherein the ADC samples the first and second amplified signals to generate first and second digital samples during conversion phases of the first and second analog-to-digital conversion cycles, respectively; and
an averaging module, connected to the ADC, that receives and averages the first and second digital samples to generate a digital output signal, wherein the averaging module eliminates the first and second sets of offset and noise signals from the digital output signal.
16. The data acquisition system of claim 15 , wherein the PGA further comprises a second amplifier, connected between the second switch and the ADC, wherein the second amplifier buffers the first and second amplified signals.
17. The data acquisition system of claim 15 , further comprising a clock source connected to the control signal generator, wherein the control signal generator generates the first and second control signals based on the clock source, and synchronizes the switching of the first control signal with the first and second analog-to-digital conversion cycles.
18. The data acquisition system of claim 15 , wherein the control signal generator comprises at least one of a finite state machine and a digital counter.
19. The data acquisition system of claim 15 , wherein the averaging module comprises at least one of an averaging filter and a combination of a digital adder and divider circuit.
20. The data acquisition system of claim 15 , wherein the first and second switches each comprise an analog multiplexer.