Area-efficient high voltage bipolar-based ESD protection targeting narrow design windows
View Patent ↗An area-efficient, high voltage, single polarity ESD protection device ( 300 ) is provided which includes an p-type substrate ( 303 ); a first p-well ( 308 - 1 ) formed in the substrate and sized to contain n+ and p+ contact regions ( 310, 312 ) that are connected to a cathode terminal; a second, separate p-well ( 308 - 2 ) formed in the substrate and sized to contain only a p+ contact region ( 311 ) that is connected to an anode terminal; and an electrically floating n-type isolation structure ( 304, 306, 307 - 2 ) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.
1. A method comprising:
providing an electrostatic discharge (ESD) protection structure in an integrated circuit formed from a semiconductor body having a substrate region of a first conductivity type wherein the ESD protection structure comprises:
(a) a first semiconductor region of the first conductivity type in which is formed a first contact region of the first conductivity type and a second contact region of a second, opposite conductivity type, where the first and second contact regions are connected to a first grounded terminal and where the first semiconductor region is sized to contain the first and second contact regions;
(b) a second semiconductor region of the first conductivity type in which is formed a third contact region of a first conductivity type without including any contact region of the second conductivity type, where the third contact region is connected to a second terminal and where the second semiconductor region is sized to contain the third contact region but not any additional contact region; and
(c) an electrically floating third semiconductor region of the second conductivity type continuous with the first and second semiconductor regions so as to surround and separate the first and second semiconductor regions; and
applying a positive voltage between the second terminal and the first grounded terminal of the integrated circuit.
2. The method of claim 1 , where the voltage arises from ESD between the first and second terminals.
3. The method of claim 1 , where the ESD protection structure enters a snap-back condition when the magnitude of the voltage across the first and second terminals becomes greater than the trigger value.
4. The method of claim 1 , where the positive voltage has a magnitude greater than a trigger value such that the voltage turns ON an npn transistor formed by the second contact region, the first semiconductor region, and the electrically floating third semiconductor region, and also turns ON a pnp transistor formed by the second semiconductor region, the electrically floating third semiconductor region, and the first semiconductor region, thereby enabling current flow through the ESD protection structure substantially only when the voltage across the first and second terminals exceeds the trigger value.
5. The method of claim 1 , where providing the ESD protection structure comprises providing a single polarity ESD clamp coupled between the first grounded terminal and the second terminal of the integrated circuit.
6. The method of claim 1 , where the first and second semiconductor regions of the first conductivity type are formed separately in the substrate region to be surrounded and separated by the electrically floating third semiconductor region of the second conductivity type such that the first semiconductor region includes the first and second contact regions of different conductivity types while the second semiconductor region includes only the third contact region of the first conductivity type with no additional contact region of the second conductivity type.
7. The method of claim 1 , where the first conductivity type is p-type, and the second conductivity type is n-type.
8. The method of claim 1 , where the first and second semiconductor regions each comprise a heavily doped p-well formed at the surface of the substrate region.
9. The method of claim 1 , where the first and second semiconductor regions each comprise a heavily doped p-well formed in a p-type epitaxial layer having relatively lighter doping.
10. The method of claim 1 , where the electrically floating third semiconductor region comprises a heavily doped n-type well formed at the surface of the substrate region to separate the first and second semiconductor regions.
11. The method of claim 10 , where the electrically floating third semiconductor region comprises a heavily doped n-type buried layer formed below the first and second semiconductor regions and in ohmic contact with the heavily doped n-type well.
12. The method of claim 10 , where the electrically floating third semiconductor region comprises an n-well region formed at the surface of the substrate region in ohmic contact with the heavily doped n-type well and separated from the first semiconductor region by a spacing dimension which controls an avalanche breakdown region between the first semiconductor region and the n-well region.
13. The method of claim 1 , where applying the positive voltage between the second terminal and the first grounded terminal of the integrated circuit comprises electrically coupling the first grounded terminal to a ground reference potential and electrically coupling the second terminal to a node in a circuit that is to be protected against a voltage exceeding a trigger voltage value such that current associated with the voltage automatically flows through the ESD protection structure when the voltage exceeding the trigger voltage value is placed across the first grounded terminal and second terminal.
14. The method of claim 1 , where the first semiconductor region is sized at a first relatively larger area to accommodate both the first and second contact regions, while the second semiconductor region is sized at a second relatively smaller area to accommodate only the third contact region.
15. The method of claim 1 , where the ESD protection structure comprises a single polarity ESD protection structure in which there are no additional contact regions for any terminal in the ESD protection structure.
16. A method for fabricating a single polarity bipolar-based electrostatic discharge protection semiconductor device, comprising:
forming separate asymmetric low and top ESD stages in an n-type semiconductor region formed in a p-type substrate, where the low ESD stage includes a p-type contact region and an n-type contact region formed in a first p-type well and electrically connected by a first grounded terminal to a ground reference potential, and where the top ESD stage includes only a p-type contact region formed in a second p-type well and electrically connected to a node in a circuit that is to be protected against a single polarity voltage exceeding a trigger voltage value.
17. The method of claim 16 , where the first p-type well is sized at a first relatively larger area, while the second p-type well is sized at a second relatively smaller area to accommodate only the p-type contact region formed in a second p-type well.
18. The method of claim 16 , further comprising applying a positive voltage between the node in the circuit that is to be protected and the first grounded terminal to trigger an inherent thyristor formed from the low and top ESD stages into a snap-back mode that provides a low impedance path through the single polarity bipolar-based electrostatic discharge protection semiconductor device for discharging the ESD current.
19. The method of claim 16 , where the n-type semiconductor region forms a base of a first PNP transistor, a collector of a first NPN transistor formed in the low ESD stage, and an n-type region of a diode formed in the top ESD stage;
where the first p-type well forms a collector of the first PNP transistor and a base of the first NPN transistor formed in the low ESD stage; where the second p-type well forms an emitter of the first PNP transistor and a p-type region of the diode formed in the top ESD stage; where the n-type contact region formed in the first p-type well forms an emitter of the first NPN transistor formed in the low ESD stage; where the p-type contact region formed in the first p-type well provides ohmic contact to the first grounded terminal for the base of the first NPN transistor formed in the low ESD stage; and where the p-type contact region formed in the second p-type well provides ohmic contact to the node in the circuit that is to be protected for the emitter of the first PNP transistor and the p-type region of the diode formed in the top ESD stage.
20. The method of claim 16 , where forming separate asymmetric low and top ESD stages in the n-type semiconductor region comprises forming a floating n-region between the first and second p-type wells to be separated from the first p-type well by a spacing dimension which controls an avalanche breakdown region between the first p-type well and the floating n-region.