Lead frame for semiconductor package with enhanced stress relief
View Patent ↗A semiconductor package includes a lead frame, a semiconductor die, bond wires providing an electrical connection between the die and the lead frame, and a mold compound that encapsulates the lead frame, the die and the bond wires. The lead frame includes spaced apart first and second frame members each having an inner peripheral edge and an opposing outer peripheral edge, spaced apart lead pads disposed between the inner peripheral edges of the first and second frame members, and conductive leads disposed proximate to the outer peripheral edge of each of the first and second frame members. The die is mounted on the lead pads.
1. A semiconductor package, comprising:
a lead frame including:
a first frame member and a second frame member spaced apart from the first frame member, each frame member having an inner peripheral edge and an opposing outer peripheral edge, a plurality of spaced apart lead pads disposed between the inner peripheral edges of the first and second frame members, wherein a first set of the plurality of spaced apart lead pads are arranged in a first row along the inner peripheral edge of the first frame member and a second set of the plurality of spaced apart lead pads are arranged in a second row along the inner peripheral edge of the second frame member, wherein the first and second rows are spaced from each other, and at least one conductive lead disposed proximate the outer peripheral edge of at least one of the first and second frame members;
a first semiconductor die mounted on at least one of the plurality of lead pads;
at least one wire providing an electrical connection between the first semiconductor die and the lead frame; and
a mold compound encapsulating the lead frame, the first semiconductor die and the at least one wire.
2. The semiconductor package of claim 1 , wherein a plurality of spaced apart conductive leads is disposed proximate the outer peripheral edges of at least one of the first and second frame members.
3. The semiconductor package of claim 2 , wherein a position of each of the plurality of spaced apart lead pads is offset from a position of each of the plurality of spaced apart conductive leads.
4. The semiconductor package of claim 1 , wherein the first set of the plurality of spaced apart lead pads are formed integrally with the first frame member and the second set of the plurality of spaced apart lead pads are formed integrally with the second frame member.
5. The semiconductor package of claim 2 , wherein the plurality of spaced apart lead pads are electrically isolated from the plurality of spaced apart conductive leads.
6. The semiconductor package of claim 1 , further comprising a second semiconductor die mounted on the first semiconductor die.
7. The semiconductor package of claim 1 , wherein at least a portion of the lead frame is half etched to facilitate mold locking.
8. The semiconductor package of claim 1 , wherein the first semiconductor die is mounted on the plurality of spaced apart lead pads and only a portion of a bottom surface of the first semiconductor die is in contact with the plurality of spaced apart lead pads.
9. The semiconductor package of claim 8 , wherein only portions of the bottom surface proximate to opposing lateral edges of the first semiconductor die are in contact with the plurality of spaced apart lead pads.
10. A lead frame for a semiconductor package, comprising:
a first frame member and a second frame member spaced apart from the first frame member, each frame member having an inner peripheral edge and an opposing outer peripheral edge, a mounting area for a semiconductor die being defined between the inner peripheral edges of the first and second frame members;
a plurality of spaced apart lead pads disposed between the inner peripheral edges of the first and second frame members in the mounting area, wherein a first set of the plurality of spaced apart leads pads are arranged in a first row along the inner peripheral edge of the first frame member and a second set of the plurality of spaced apart lead pads are arranged in a second row along the inner peripheral edge of the second frame member, wherein the first and second rows are spaced from each other; and
a plurality of spaced apart conductive leads disposed proximate the outer peripheral edge of at least one of the first and second frame members.
11. The lead frame of claim 10 , wherein a position of each of the plurality of spaced apart lead pads is offset from a position of each of the plurality of spaced apart conductive leads.
12. The lead frame of claim 10 , wherein the first set of the plurality of spaced apart conductive leads are arranged in a third row along the outer peripheral edge of the first frame member and the second set of the plurality of spaced apart conductive leads are arranged in a fourth row along the outer peripheral edge of the second frame member.
13. The lead frame of claim 10 , wherein each of the plurality of spaced apart lead pads is configured to receive a semiconductor die thereon.
14. The lead frame of claim 10 , wherein the first set of the plurality of spaced apart lead pads are formed integrally with the first frame member and the second set of the plurality of spaced apart lead pads are formed integrally with the second frame member.
15. The lead frame of claim 10 , wherein at least a portion of the lead frame is half etched to facilitate mold locking.
16. The lead frame of claim 15 , wherein at least one of the plurality of spaced apart lead pads and at least one of the plurality of conductive leads are half etched to facilitate mold locking.
17. A semiconductor package, comprising:
a lead frame including:
a first frame member and a second frame member spaced apart from the first frame member, each frame member having an inner peripheral edge and an opposing outer peripheral edge,
a first set of spaced apart lead pads integrally formed with the first frame member and being arranged in a first row adjacent the inner peripheral edge of the first frame member,
a second set of spaced apart lead pads integrally formed with the second frame member and being arranged in a second row adjacent the inner peripheral edge of the second frame member, and
a plurality of spaced apart conductive leads disposed along the outer peripheral edges of each of the first and second frame members;
a first semiconductor die having a top surface and a bottom surface, the first semiconductor die being mounted on the plurality of spaced apart lead pads such that a portion of the bottom surface is in contact with the plurality of spaced apart lead pads;
a second semiconductor die mounted on the top surface of the first semiconductor die;
a first set of bond wires each having a first end bonded to the first semiconductor die and a second end bonded to the second semiconductor die, the first set of bond wires providing an electrical connection between the first semiconductor die and the second semiconductor die;
a second set of bond wires each having a first end bonded to one of the plurality of spaced apart conductive leads and a second end bonded to the second semiconductor die, the second set of bond wires providing an electrical connection between the conductive leads and the second semiconductor die; and
a mold compound encapsulating the lead frame, the first and second semiconductor dies, and the first and second sets of bond wires.
18. The semiconductor package of claim 17 , wherein another portion of the bottom surface of the first semiconductor die does not contact the plurality of spaced apart lead pads.