IP Library Granted Patent US 8,884,358
Granted Patent B2
US 8,884,358 · App. 13/748,808 · Granted Nov 11, 2014

Method of making a non-volatile memory (NVM) cell structure

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Quick Facts
Patent No.
US 8,884,358
App. No.
13/748,808
Granted
Nov 11, 2014
Kind
B2
Abstract

A non-volatile memory device includes a substrate and a charge storage layer. The charge storage layer comprises a bottom layer of oxide, a layer of discrete charge storage elements on the bottom layer of oxide, and a top layer of oxide on the charge storage elements. A control gate is on the top layer of oxide. A surface of the top layer of oxide facing a surface of the control gate is substantially planar.

Claims (32)

1. A non-volatile memory device comprising:

a substrate;

a charge storage layer comprising:

a bottom layer of oxide;

a layer of discrete charge storage elements on the bottom layer of oxide;

a top layer of oxide on the discrete charge storage elements; and

a control gate on the top layer of oxide, wherein a surface of the top layer of oxide facing a surface of the control gate is substantially planar, and wherein a radius of curvature of the top layer of oxide over a majority of the discrete charge storage elements is at least twice a sum of a radius of the discrete charge storage element plus a thickness of the top layer of oxide.

2. The device of claim 1 , further comprising:

a select gate, wherein a portion of: the bottom layer of oxide, the discrete charge storage elements, and the top layer of oxide, are between one side of the control gate and one side of the select gate.

3. The device of claim 1 , further comprising:

a thin layer of oxide on an outer surface of the charge storage elements.

4. The device of claim 1 , further comprising:

a thickness of the top layer of oxide over at least one of the charge storage elements is less than a diameter of the at least one charge storage element.

5. A method of making a non-volatile memory device comprising:

forming a first electrically insulating material on a substrate;

forming discrete charge storage elements on the first electrically insulating material; and

depositing a second electrically insulating material over the discrete charge storage elements, wherein a top surface of the second electrically insulating material is substantially planar, wherein a radius of curvature of the second electrically insulating material over one of the discrete charge storage elements is at least twice a sum of a radius of the one discrete charge storage element plus a thickness of the second electrically insulating material.

6. The method of claim 5 , further comprising forming a control gate over the second electrically insulating material.

7. The method of claim 5 , further comprising forming a select gate over a third insulating material.

8. The method of claim 5 , further comprising growing an oxide layer on the discrete charge storage elements before depositing the second electrically insulating material.

9. The method of claim 5 , wherein a thickness of the second electrically insulating material over at least one of the discrete charge storage elements is less than a diameter of the at least one discrete charge storage element.

10. The method of claim 5 , further comprising chemically-mechanically polishing the second electrically insulating material to be substantially planar.

11. The method of claim 5 , further comprising depositing a conformal layer of electrically insulating material on the discrete charge storage elements before depositing the second electrically insulating material.

12. The method of claim 5 , further comprising etching the second electrically insulating material to be substantially planar.

13. A method comprising:

forming a first oxide layer on a substrate;

forming discrete charge storage elements on the first oxide layer; and

forming a second oxide layer that is planar on the discrete charge storage elements having a thickness that is less than a diameter of the charge storage elements, wherein a radius of curvature of the second oxide layer over the discrete charge storage elements is at least twice a sum of a radius of the discrete charge storage elements plus a thickness of the second oxide layer.

14. The method of claim 13 , wherein the diameter of the discrete charge storage elements is between 10 to 20 nanometers and the thickness of the second oxide layer over the charge storage elements is between 6 and 10 nanometers.

15. The method of claim 13 , further comprising depositing a conformal oxide layer on the charge storage elements before depositing the second oxide layer.

16. The method of claim 13 , further comprising chemically-mechanically polishing the second oxide layer.

17. The method of claim 13 , further comprising etching the second oxide layer.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0704 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0744 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0725 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2013
From: WINSTEAD, BRIAN A.; KANG, SUNG-TAEG; RUSSOW, MARC A.
To: FREESCALE SEMICONDUCTOR, INC.
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