Data processor device for handling a watchpoint and method thereof
View Patent ↗During a debug mode of operation of a data processor, it is determined at the data processor that a watchpoint event has occurred, and in response, an operating condition of a trace FIFO that stores trace information not yet communicated to a debugger is changed. For example, the occurrence of a FIFO flush watchpoint results in trace information being selectively flushed from the trace FIFO based on a state of the FIFO before the trace information has been communicated to a trace analyzer.
1. A method comprising:
enabling a debug trace mode of operation of an integrated circuit;
storing first trace information at a memory of the integrated circuit in response to the debug trace mode of operation being enabled; and
in response to a flush request signal, responsive to detecting an occurrence of a watchpoint, flushing the first trace information from the memory to prevent the first trace information from being provided for trace analysis if the memory is filled with the trace information to a specified fill level, wherein detecting the occurrence of the watchpoint occurs after storing of the first trace information.
2. The method of claim 1 , wherein the specified level is one of a group of different levels.
3. The method of claim 1 further comprising:
retaining the trace information in the memory if the memory is not filled with the trace information to the specified level.
4. The method of claim 1 further comprising:
generating a trace message that indicates the occurrence of the watchpoint.
5. The method of claim 1 , wherein new trace information is not stored at the memory during the debug trace mode of operation in response to the memory being full.
6. The method of claim 1 further comprising:
enabling the trace mode is in response to detecting occurrence of a watchpoint of a first type or a second type.
7. The method of claim 1 further comprising: receiving a command at an interface of the integrated circuit, and enabling the trace mode in response to executing the command.
8. The method of claim 1 , wherein flushing the trace information from the memory in response to detecting the occurrence of a watchpoint includes asserting a memory flush indicator.
9. The method of claim 1 , wherein the occurrence of the watchpoint is detected in response to an address of an access matching an address associated with the watchpoint.
10. A device comprising:
an integrated circuit comprising a debug trace module, the debug trace module coupled to provide trace information of a data processor to a memory module;
a watchpoint module to provide a flush request indicator in response to detecting an occurrence of a watchpoint event; and
the memory module coupled to provide a trace information level indicator to the watchpoint module, the memory module to flush the trace information stored at the memory module so that the trace information is prevented from being provided for trace analysis in response to the flush request indicator and the trace information level indicator being greater than or equal to a specified fill level.
11. The device of claim 10 , wherein the memory module is a first-in first-out memory.
12. The device of claim 10 , wherein the trace module is coupled to the watchpoint module, and generates a trace message indicative of the flush indicator being provided.
13. The device of claim 10 , wherein the trace message indicative of the flush indicator being provided is to be stored at the memory module subsequent to the buffered trace information being flushed.
14. The device of claim 10 , wherein the memory module does not store new trace information in response to the memory being full.
15. The device of claim 10 , wherein the watchpoint event is a first watchpoint event of a first type, and the watchpoint module to provide a trace enable indicator at the output in response to detecting an occurrence of a second watchpoint event of a second type, and the trace module is enabled to provide the trace information for trace analysis in response to the trace enable indicator.
16. The method of claim 10 , wherein the specified level is one of a group of different levels.
17. A method comprising:
enabling detection of a trace FIFO control watchpoint event, wherein a trace FIFO control watchpoint is to modify operation of a FIFO (First-in First-out) memory that stores trace information of a data processor's operation;
in response to detecting an occurrence of the trace FIFO control watchpoint, modifying an operating condition of the FIFO from a first operating condition to a second operating condition if a level indicator of trace information in the FIFO memory is greater than a specified fill level, wherein the second operating condition varies from the first operating condition in that trace information in the FIFO memory during the first operating condition has been flushed, in response to a flush request signal based upon the occurrence of the trace FIFO control watchpoint, to prevent the trace information from being provided for trace analysis at the second operating condition, and the FIFO memory is enabled to store additional trace information during both the first and second operating conditions.
18. The method of claim 17 further comprising: generating trace information indicative of the modification of the operating condition of the FIFO.
19. The method of claim 18 , wherein the trace information is stored at the FIFO.