Bus signal encoded with data and clock signals
View Patent ↗A CODEC includes a transmission path between an encoder and a decoder. The encoder receives bits of data in a first form in which each bit of the data is represented by switching between first and second logic states and no voltage change between consecutive bits of the same logic state and serially transmits the bits in a second form in which the first logic state is maintained at a high voltage, the second logic state is maintained at a low voltage, and an intermediate voltage is maintained between consecutive bits. The decoder receives the bits in the second form and derives a clock from the occurrences of the intermediate voltage. The clock, repetitively, is maintained at a logic high, then switches directly from the logic high to a logic low, then is maintained at the logic low, and then switches directly between the logic low and the logic high.
1. A codec, comprising:
a data and clock encoder that receives bits of data in a first form in which each bit of the data is represented by one of a first logic state and a second logic state and transmits the bits of data serially in a second form in which the first logic state of a bit is represented by maintaining a high voltage and the second logic state of a bit is represented by maintaining a low voltage and an intermediate voltage is maintained between adjacent bits of the bits of data transmitted serially;
a transmission path coupled to the data and clock encoder that transmits the bits of data in the second form; and
a data and clock decoder coupled to the transmission path that receives the bits of data transmitted in the second form and derives a clock from the intermediate voltage that is maintained between adjacent bits that repetitively:
is maintained at a logic high;
then switches directly from the logic high to a logic low,
then is maintained at the logic low; and
then switches directly between the logic low and the logic high.
2. The codec of claim 1 , wherein the data and clock decoder is further characterized as converting the bits of data transmitted serially to sequential bits in which the sequential bits are adjacent so that a voltage level is maintained when adjacent bits are the same logic state and the voltage level is changed when adjacent bits have a different logic state.
3. The codec of claim 2 , wherein the sequential bits have a data rate and the clock has a clock rate, wherein the clock rate and the data rate are the same and the data and clock encoder, the transmission path, and the data and clock decoder are on the same integrated circuit.
4. The codec of claim 2 further comprising:
a register having a plurality of data outputs;
a multiplexer having inputs coupled to the plurality of outputs of the register and an output coupled to the data and clock encoder,
wherein:
the multiplexer provides the bits of data to the data and clock encoder as a result of multiplexing the plurality of outputs of the register.
5. The codec of claim 4 , further comprising a demultiplexer coupled to the data and clock decoder, wherein the demultiplexer separates the sequential bits into a plurality of data streams corresponding to the plurality of data outputs of the register.
6. The codec of claim 1 , wherein the data and clock encoder comprises:
a first inverter having an input for receiving an input clock and an output;
a second inverter having an input coupled to the output of the first inverter and an output;
a tristate driver with a control input coupled to the input of the second inverter, an input for receiving the bits of data, and an output coupled to the transmission path; and
a transistor having a control electrode coupled to the output of the first inverter, a first current electrode coupled to an intermediate power supply terminal that has an output at a voltage level equal to the intermediate voltage level, and a second current electrode coupled to the output of the third inverter.
7. The codec of claim 1 , wherein the data and clock decoder comprises:
a data regenerator having an input coupled to the transmission path, a first output, and a second output; and
a separator circuit for generating the clock and providing sequential bits representative of the bits of data in response to the first output and the second output.
8. The codec of claim 7 , wherein the data regenerator comprises:
a capacitor having a first terminal coupled to the transmission path and a second terminal;
an inverter having an input coupled to second terminal of the capacitor and an output;
a bias circuit coupled to the input of the inverter for biasing the input of the inverter to a voltage between the high voltage and the low voltage;
a first transmission gate having a complementary input coupled to the output of the inverter, a first terminal coupled to the transmission path, and a second terminal coupled to the first output of the data regenerator; and
a second transmission gate having a true input coupled to the output of the inverter, a first terminal coupled to the transmission path, and a second terminal coupled to the second output of the regenerator circuit.
9. The codec of claim 7 , wherein the separator circuit comprises:
a latch circuit coupled to the first and second outputs of the regenerator circuit that provides the sequential bits in which the sequential bits are adjacent so that a voltage level is maintained when adjacent bits are the same logic state and the voltage level is changed when adjacent bits have a different logic state; and
a NOR gatecoupled to the first and second outputs of the regenerator circuit, wherein the NOR gate outputs a clock signal.
10. The codec of claim 8 , wherein the regenerator further comprises a detector inverter ( 822 ), the detector inverter is used to couple the second terminal of the first transmission gate to first output of the regenerator, wherein the detector inverter has an input coupled to the second terminal of the first transmission gate and an output coupled to the first output of the regenerator circuit.
11. A method of operating a codec in transmitting data across a transmission path of the codec, comprising:
formatting sequential bits of data from a first form in which each bit of the data is represented by one of a first logic state and a second logic state to a form in which the first logic state of a bit is represented by maintaining a high voltage and the second logic state of a bit is represented by maintaining a low voltage and an intermediate voltage is maintained between adjacent bits of the bits of data;
transmitting the bits of data in the second form across the transmission path; and
receiving the bits of data transmitted in the second form; and
deriving a clock from the intermediate voltage that is maintained between adjacent bits.
12. The method of claim 11 , further comprising, after transmitting the bits of data, converting the bits of data to sequential bits into received sequential bits the first form.
13. The method of claim 12 , wherein the received sequential bits have a data rate and the clock has a clock rate, wherein the clock rate and the data rate are the same.
14. The method of claim 11 , further comprising providing a plurality of data outputs in the first form.
15. The method of claim 11 , whereby, in the formatting the bits in the first form, adjacent bits at the same logic state in the first form have no change in voltage between the adjacent bits.
16. A codec, comprising:
an encoder that receives bits in a first form of one of a first logic state and a second logic state in which no transition in voltage occurs between consecutive bits when the consecutive bits are both of the first logic state or of the second logic state and has an output that provides the bits in a second form in which an intermediate voltage is maintained between consecutive bits that is intermediate a voltage of the first logic state and a voltage of the second logic state;
a transmission path having a first end coupled to the output of the encoder, wherein the transmission path has a second end;
a decoder coupled to the second end that generates a regenerated clock responsive to occurrences of the intermediate voltage.
17. The codec of claim 16 , wherein the decoder is further characterized as providing a serial data stream synchronized with the recovered clock.
18. The method of claim 16 , wherein, in the second form, the first logic state is a positive voltage, the second logic state is a negative voltage, and the intermediate voltage is ground.
19. The method of claim 16 , wherein, in the second form, the first logic state is a positive voltage, the second logic state is a ground, and the intermediate voltage is approximately ½ VDD.
20. The codec of claim 16 further comprising:
a register having a plurality of data outputs;
a multiplexer having inputs coupled to the plurality of outputs of the register and an output coupled to the encoder,
wherein:
the multiplexer provides the bits of data to the encoder as a result of multiplexing the plurality of outputs of the register.