Packaged semiconductor device
View Patent ↗A packaged semiconductor device includes a substrate including a first major surface, a second major surface, first vias running between the first major surface and the second major surface, first contact pads contacting the first vias at the first major surface, second contact pads contacting the first vias at the second major surface, and an opening between the first major surface and the second major surface. A first integrated circuit (IC) die is positioned in the opening in the substrate. Electrical connections are formed between the second IC die and the second contact pads. A first conductive layer is over the first contact pads and contact pads on the first IC die. Encapsulating material is on the second major surface of the substrate around the first IC die, the second IC die, the electrical connections, and between edges of the opening and edges of the first IC die.
1. A packaged semiconductor device, comprising:
a first integrated circuit die positioned in an opening in a circuit board, the first integrated circuit die having an active surface facing a same direction as a first major surface of the circuit board, the circuit board further comprising a second major surface, first vias running between the first major surface and the second major surface, first contact pads contacting the first vias at the first major surface, second contact pads contacting the first vias at the second major surface, the opening extending through the first major surface and the second major surface;
a second integrated circuit die adjacent a non-active surface of the first integrated circuit die;
wire bonds between the second integrated circuit die and the second contact pads;
a continuous body of encapsulant material around the first and second integrated circuit dies, the wire bonds, and the second contact pads, the encapsulant material extending from sides of the first integrated circuit die to sides of the opening in contact with the first major surface and the second major surface, the active surface of the first integrated circuit die remaining free of the encapsulant material;
a first conductive layer over the first major surface contacting the first contact pads and contact pads on the active surface of the first integrated circuit die.
2. The device of claim 1 , further comprising:
solder balls between an electrical device and the first contact pads.
3. The device of claim 1 , further comprising:
additional conductive layers separated by interlevel dielectric layers over the first conductive layer, the additional conductive layers being interconnected with vias.
4. The device of claim 3 , further comprising solder balls connected to contact pads at a last level of the additional levels.
5. The device of claim 1 , wherein the circuit board includes third contact pads on the first major surface and fourth contact pads on the second major surface, the device further comprising:
a solder bump attached to each of the fourth contact pads.
6. The device of claim 1 , wherein the circuit board includes third contact pads on the second major surface, the device further comprising:
a non-active surface of a third integrated circuit die attached to an active surface of the second integrated circuit die;
electrical connections formed between the third integrated circuit die and the third contact pads.
7. The device of claim 6 , wherein the circuit board has second vias that extend between the first major surface and the second major surface, the third contact pads terminate the second vias at the second major surface, and fourth contact pads terminate the second vias at the first major surface.
8. A packaged semiconductor device, comprising:
a substrate including a first major surface, a second major surface, first vias running between the first major surface and the second major surface, first contact pads contacting the first vias at the first major surface, second contact pads contacting the first vias at the second major surface, and an opening between the first major surface and the second major surface;
a first integrated circuit die in the opening in the substrate, wherein planform area of the opening is larger than planform area of the first integrated circuit die;
a second integrated circuit die;
electrical connections between the second integrated circuit die and the second contact pads;
a first conductive layer over the first contact pads and contact pads on a first surface of the first integrated circuit die; and
a continuous body of encapsulating material in contact with the first major surface and the second major surface of the substrate around a second surface and side surfaces of the first integrated circuit die, the second integrated circuit die, the electrical connections, and in space between edges of the opening and edges of the first integrated circuit die.
9. The device of claim 8 further comprising:
additional conductive layers over the first conductive layer including a plurality of levels of conductive layers interconnected with vias through interlevel dielectric layers; and
a last conductive layer with contacts for connecting the device to another component external to the device.
10. A packaged semiconductor device, comprising:
a first semiconductor die in an opening of a substrate, wherein
the first semiconductor die has an active surface and a non-active surface, and
the substrate has a first major surface and a second major surface which have the opening therethrough, first vias that extend between the first major surface and the second major surface, first contact pads terminating the first vias at the first major surface, and second contact pads terminating the first vias at the second major surface;
a continuous body of encapsulant material in contact with the first major surface and the second major surface, and in the opening around the first semiconductor die while leaving electrical contacts on the active surface of the first semiconductor die free of the encapsulant material;
a non-active surface of a second semiconductor die attached adjacent the non-active surface of the first semiconductor die;
electrical connections between an active surface of the second semiconductor die and the second contact pads;
the encapsulant material further around exposed portions of the second semiconductor die, the electrical connections, and the second contact pads;
a first conductive layer of an interconnect level over the first contact pads of the first major surface and contact pads on the active surface of the first semiconductor die.
11. The device of claim 10 , wherein the encapsulant material is between sidewalls of the first semiconductor die and sidewalls of the opening.
12. The device of claim 10 , further comprising:
a first dielectric layer over the first conductive layer; and
openings in the dielectric layer for a plurality of vias.
13. The device of claim 12 , further comprising alternating conductive and dielectric layers at a plurality of levels from the first dielectric layer.
14. The device of claim 10 , wherein the substrate includes third contact pads on the second major surface, the device further comprising:
a non-active surface of a third semiconductor die attached to an active surface of the second semiconductor die;
electrical connections between the third semiconductor die and the third contact pads.
15. The device of claim 14 , further comprising solder balls connected to contact pads at a last level of the plurality of levels.
16. The device of claim 14 , wherein the substrate has second vias that extend between the first major surface and the second major surface, the third contact pads terminating the second vias at the second major surface, and fourth contact pads terminating the second vias at the first major surface.
17. The device of claim 10 , wherein the substrate includes third contact pads on the second major surface, the device further comprising:
connecting solder sumps to the third contact pads.