Systems and methods for reduced coupling between digital signal lines
View Patent ↗Methods and systems are disclosed for reduced coupling between digital signal lines. For disclosed embodiments, return-to-zero signaling is dynamically blocked so that high logic levels remain high through entire clock cycles where the next data to be output is also at high logic levels. The dynamically blocked return-to-zero signaling reduces capacitive coupling between digital signal lines, such as clock and data signal lines, that are in close proximity to each other by reducing current flow that would otherwise occur with return-to-zero signaling. The dynamically blocked return-to-zero signaling can be used in a wide variety of environments and implementations.
1. A digital data output system, comprising:
data storage circuitry configured to store two or more data bits and to output the data bits in sequence based upon a clock signal; and
output circuitry coupled to receive a current data bit and a next data bit from the data storage circuitry;
wherein the output circuitry is configured to output a low logic level for a clock cycle when the current data bit is a low logic level; and
wherein the output circuitry is further configured to output a high logic level during a first portion of a clock cycle when the current data bit is a high logic level, to maintain the high logic level for the clock cycle if the next data bit is a high logic level, and to transition to a low logic level during the clock cycle if the next data bit is a low logic level.
2. The digital data output system of claim 1 , wherein the output circuitry is configured to output the high logic level on a first clock edge for the clock cycle and to output the low logic level on a second clock edge for the clock cycle when the current data bit is a high logic level and the next data bit is a low logic level.
3. The digital data output system of claim 2 , wherein the first clock edge is a rising edge and the second clock edge is a falling edge.
4. The digital data output circuitry of claim 1 , wherein the data storage circuitry comprises a current data register configured to output the current data bit and a next data register configured to output the next data bit.
5. The digital data output system of claim 1 , wherein the output circuitry is configured to output the high logic level for an entire clock cycle when the current data bit is a high logic level and the next data bit is a high logic level.
6. The digital data output system of claim 1 , wherein the output circuitry comprises return-to-zero circuitry configured to receive current data bits and to output return-to-zero logic levels, and wherein the output circuitry further comprises block circuitry configured to selectively output a logic level associated with a current data bit or a return-to-zero logic level based upon a block control signal.
7. The digital data output signal of claim 6 , wherein the output circuitry further comprises control circuitry configured to receive the current data bit and the next data bit, to assert the block control signal if the current data bit and the next data bit are both at a high logic level, and to de-assert the block control signal if the current data bit or the next data bit is at a low logic level.
8. The digital data output system of claim 1 , wherein the data storage circuitry comprises a buffer configured to receive the two or more data bits at a first clock rate and to output the two or more data bits at a second clock rate, the second clock rate being associated with the clock signal.
9. The digital data output system of claim 8 , wherein the buffer comprises a first-in-first-out buffer.
10. The digital data output system of claim 1 , wherein the data storage circuitry comprises a cache buffer configured to receive the two or more data bits from system bus circuitry and to output the two or more data bits for a cache memory based upon the clock signal.
11. A method for outputting digital data, comprising:
storing two or more data bits to be output in sequence based upon a clock signal;
determining a logic level for a current data bit;
outputting a low logic level for a clock cycle if the current data bit is a low logic level; and
outputting a high logic level for a first portion of a clock cycle if the current data bit is a high logic level, maintaining the high logic level for the clock cycle if the next data bit is a high logic level, and transitioning to a low logic level during the clock cycle if the next data bit is a low logic level; and
repeating the determining and outputting steps for a plurality of clock cycles to output the two or more stored data bits in sequence.
12. The method of claim 11 , wherein when the current data bit is a high logic level and the next data bit is a low logic level, the method includes outputting a high logic level on a first clock edge for the clock cycle and a low logic level on a second clock edge for the clock cycle.
13. The method of claim 12 , wherein the first clock edge is a rising edge and the second clock edge is a falling edge.
14. The method of claim 11 , wherein the storing step comprising storing the current data bit in a current data register and storing the next data bit in a next data register.
15. The method of claim 11 , wherein when the current data bit is a high logic level and the next data bit is a high logic level, outputting the high logic level for an entire clock cycle.
16. The method of claim 11 , wherein the outputting steps comprise using return-to-zero circuitry to receive current data bits and to output return-to-zero logic levels, and selectively outputting a logic level associated with a current data bit or a return-to-zero logic level based upon a block control signal.
17. The method of claim 16 , further comprising asserting the block control signal if the current data bit and the next data bit are both at a logic high level, and de-asserting the block control signal if the current data bit or the next data bit is at a low logic level.
18. The method of claim 11 , wherein the storing step comprises storing the two or more data bits in a buffer at a first clock rate that is different from a second clock rate associated with the clock signal.
19. The method of claim 11 , wherein the buffer comprises a first-in-first-out buffer.
20. The method of claim 11 , wherein the storing step comprises storing the two or more data bits in a cache buffer, the two or more data bits being received from system bus circuitry.