IP Library Granted Patent US 9,424,200
Granted Patent B2
US 9,424,200 · App. 13/842,516 · Granted Aug 23, 2016

Continuous run-time integrity checking for virtual memory

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Quick Facts
Patent No.
US 9,424,200
App. No.
13/842,516
Granted
Aug 23, 2016
Kind
B2
Abstract

A run-time integrity checking (RTIC) method compatible with memory having at least portions that store data that is changed over time or at least portions configured as virtual memory is provided. For example, the method may comprise storing a table of page entries and accessing the table of page entries by, as an example, an operating system or, as another example, a hypervisor to perform RTIC on memory in which, as an example, an operating system, as another example, a hypervisor, or, as yet another example, application software is stored. The table may, for example, be stored in secure memory or in external memory. The page entry comprises a hash value for the page and a hash valid indicator indicating the validity status of the hash value. The page entry may further comprise a residency indicator indicating a residency status of the memory page.

Claims (40)

1. A method for run-time integrity checking (RTIC) of a virtual memory system comprising:

calculating a chained overall hash value dependent on preceding memory page hash values corresponding to preceding ones of a plurality of memory pages, the chained overall hash value being chained such that a first preceding memory page hash value corresponding to a first preceding one of the plurality of memory pages is concatenated with a second preceding one of the plurality of memory pages and a second preceding memory page hash value is calculated, with concatenation and hash generation continuing for each block to yield the chained overall hash value;

storing a table of page entries, wherein a page entry of the page entries corresponds to a memory page of the plurality of memory pages into which the virtual memory system is organized, wherein the page entry comprises a reference hash value for the page and a hash valid indicator indicating the validity status of the reference hash value; and

accessing the table of page entries by a run-time integrity checking system to perform the RTIC of the memory page referenced by the table of the page entries when the memory page is present in physical memory; and

inhibiting the RTIC of the memory page in response to the memory page being swapped out of the physical memory into storage.

2. The method of claim 1 wherein the table is stored in secure memory.

3. The method of claim 1 wherein the table is stored in external memory.

4. The method of claim 1 wherein the page entry further comprises:

a residency indicator indicating a residency status of the memory page.

5. The method of claim 1 further comprising:

inhibiting writing a hash value to the page entry of the table in response to the hash valid indicator indicating that the reference hash value in the page entry is valid.

6. The method of claim 1 further comprising:

calculating an overall hash value from a plurality of memory page hash values corresponding to the plurality of memory pages.

7. The method of claim 1 wherein the memory referenced by the table of the page entries stores instruction code for an operating system.

8. A method for run-time integrity checking (RTIC) of a virtual memory system comprising:

calculating a chained overall hash value dependent on preceding memory page hash values corresponding to preceding ones of a plurality of memory pages, the chained overall hash value being chained such that a first preceding memory page hash value corresponding to a first preceding one of the plurality of memory pages is concatenated with a second preceding one of the plurality of memory pages and a second preceding memory page hash value is calculated, with concatenation and hash generation continuing for each block to yield the chained overall hash value;

storing a table of page entries by a hypervisor, wherein a page entry of the page entries corresponds to a memory page of the plurality of memory pages into which the virtual memory system is organized, wherein the page entry comprises a reference hash value for the page and a hash valid indicator indicating the validity of the reference hash value; and

accessing the table of page entries by a run-time integrity checking system to perform the RTIC of the memory page in which the hypervisor is stored.

9. The method of claim 8 wherein the page entry further comprises:

a residency indicator indicating a residency status of the memory page.

10. A method for run-time integrity checking (RTIC) of virtual memory system comprising:

calculating a chained overall hash value dependent on preceding memory page hash values corresponding to preceding ones of a plurality of memory pages, the chained overall hash value being chained such that a first preceding memory page hash value corresponding to a first preceding one of the plurality of memory pages is concatenated with a second preceding one of the plurality of memory pages and a second preceding memory page hash value is calculated, with concatenation and hash generation continuing for each block to yield the chained overall hash value;

storing a table of page entries, wherein a page entry of the page entries corresponds to a memory page of the plurality of memory pages into which the virtual memory system is organized, wherein the page entry comprises a reference hash value for the page and a hash valid indicator indicating the validity status of the reference hash value;

accessing the page entry;

in response to the accessing the page entry, performing the run-time integrity checking of the memory page;

beginning execution of a software entity comprising information stored in the memory page;

performing a second instance of the run-time integrity checking of the memory page after the execution of the software entity has begun; and

inhibiting the run-time integrity checking of the memory page in response to the memory page being swapped out of physical memory into storage.

11. The method of claim 10 wherein performing the second instance of the run-time integrity checking is performed while the information remains stored in the memory page.

12. The method of claim 10 wherein performing the second instance of the run-time integrity checking is performed before execution of the software entity ends.

13. The method of claim 10 wherein the table is stored in secure memory.

14. The method of claim 10 wherein the table is stored in external memory.

15. The method of claim 10 wherein the page entry further comprises:

a residency indicator indicating a residency status of the memory page.

16. The method of claim 10 further comprising:

inhibiting writing a hash value to the page entry of the table in response to the hash valid indicator indicating that the reference hash value in the page entry is valid.

17. The method of claim 10 further comprising:

writing the hash value to the page entry of the table in response to the hash valid indicator indicating that the reference hash value in the page entry is not valid.

18. The method of claim 10 further comprising:

calculating an overall hash value from a plurality of memory page hash values corresponding to the plurality of memory pages.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0744 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2013
From: TKACIK, THOMAS E.; BROCKER, MATTHEW W.; COVEY, CARLIN R.
To: FREESCALE SEMICONDUCTOR, INC.
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