Granted Patent B1

US 8,527,935 · App. 13/735,049 · Granted Sep 3, 2013

Abstract

Claims (29)

1. An electronic design automation (EDA) tool for reducing power consumption of an electronic circuit design, wherein the circuit design includes a plurality of digital logic elements, the EDA tool comprising:

a memory used to store the electronic circuit design; and

a processor, in communication with the memory, and configured to:

generate a look-up table (LUT) for storing a mapping between a type, a predetermined optimum power input transition time and at least one characteristic of each digital logic element in a cell library, wherein the predetermined optimum power input transition time of a digital logic element corresponds to a lowest sum of a switching power and a short circuit power of the digital logic element, wherein at the predetermined optimum power input transition time, the switching power and short circuit power of the digital logic element are equal;

identify an input transition time of a first digital logic element; and

replace the first digital logic element with a second digital logic element when the input transition time of the first digital logic element is not equal to the predetermined optimum power input transition time of the first digital logic element, wherein the second digital logic element has a predetermined optimum power input transition time equal to the input transition time of the first digital logic element.

2. The EDA tool of claim 1 , wherein the at least one characteristic includes an output load, a size, a strength and a sum of a switching power and a short circuit power of each digital logic element.

3. The EDA tool of claim 1 , wherein the type of a digital logic element includes one of an AND gate, an OR gate, a NOT gate, a NOR gate, a NAND gate, an XOR gate, an XNOR gate, and a combinational logic circuit.

4. The EDA tool of claim 1 , wherein the processor further determines first and second timing delays corresponding to the first and second digital logic elements.

5. The EDA tool of claim 4 , wherein the processor further replaces the second digital logic element with a third digital logic element when the second timing delay is greater than the first timing delay, wherein the third digital logic element has a predetermined optimum power input transition time that is substantially equal to the input transition time of the first digital logic element.

6. The EDA tool of claim 5 , wherein the second and third digital logic elements are selected, by matching a type and at least one characteristic of the second and third digital logic elements with a type and at least one characteristic of the first digital logic element, respectively.

7. A method for reducing power consumption of an electronic circuit design that includes a plurality of digital logic elements, using an electronic design automation (EDA) tool, wherein the EDA tool includes a memory that stores the electronic circuit design and a processor in communication with the memory, the method comprising:

generating a look-up table (LUT) storing a mapping between a type, a predetermined optimum power input transition time, and at least one characteristic of each digital logic element in a cell library, wherein the predetermined optimum power input transition time of a digital logic element corresponds to a lowest sum of a switching power and a short circuit power of the digital logic element, wherein at the predetermined optimum power input transition time, the switching power and short circuit power of the digital logic element are equal;

identifying an input transition time of a first digital logic element; and

replacing the first digital logic element with a second digital logic element when the input transition time of the first digital logic element is not equal to the predetermined optimum power input transition time of the first digital logic element, wherein the second digital logic element has a predetermined optimum power input transition time equal to the input transition time of the first digital logic element.

8. The method of claim 7 , wherein the at least one characteristic includes an output load, a size, a strength and a sum of a switching power and a short circuit power of each digital logic element.

9. The method of claim 7 , wherein the type of a digital logic element includes one of an AND gate, an OR gate, a NOT gate, a NOR gate, a NAND gate, an XOR gate, an XNOR gate, and a combinational logic.

10. The method of claim 7 , further comprising determining first and second timing delays corresponding to the first and second digital logic elements.

11. The method of claim 10 , further comprising replacing the second digital logic element with a third digital logic element when the second timing delay is greater than the first timing delay, wherein the third digital logic element has a predetermined optimum power input transition time substantially equal to the input transition time of the first digital logic element.

12. The method of claim 11 , wherein the second and third digital logic elements are selected, by matching a type and at least one characteristic of the second and third digital logic elements with a type and at least one characteristic of the first digital logic element, respectively.

13. A method for reducing power consumption of an electronic circuit design that includes a plurality of digital logic elements, using an electronic design automation (EDA) tool, wherein the EDA tool includes a memory that stores the electronic circuit design and a processor in communication with the memory, the method comprising:

generating a look-up table (LUT) storing a mapping between a type, a predetermined optimum power input transition time and at least one characteristic of each digital logic element in a cell library, wherein the predetermined optimum power input transition time of a digital logic element corresponds to a lowest sum of a switching power and a short circuit power of the digital logic element, wherein at the predetermined optimum power input transition time, the switching power and short circuit power of the digital logic element are equal;

identifying an input transition time of a first digital logic element;

replacing the first digital logic element with a second digital logic element when the input transition time of the first digital logic element is not equal to the predetermined optimum power input transition time of the first digital logic element, wherein the second digital logic element has a predetermined optimum power input transition time equal to the input transition time of the first digital logic element;

determining first and second timing delays corresponding to the first and second digital logic elements; and

replacing the second digital logic element with a third digital logic element when the second timing delay is greater than the first timing delay, wherein the third digital logic element has a predetermined optimum power input transition time substantially equal to the input transition time of the first digital logic element.

14. The method of claim 13 , wherein the at least one characteristic includes an output load, a size, a strength and a sum of a switching power and a short circuit power of each digital logic element.

15. The method of claim 13 , wherein the type of a digital logic element includes one of an AND gate, an OR gate, a NOT gate, a NOR gate, a NAND gate, an XOR gate, an XNOR gate, and a combinational logic.

16. The method of claim 13 , wherein the second and third digital logic elements are selected, by matching a type and at least one characteristic of the second and third digital logic elements with a type and at least one characteristic of the first digital logic element, respectively.

Assignments (17)